Xilinx Virtex-5 RocketIO GTP User Manual

224 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Chapter 11: Design Constraints Overview
R
closure. See Chapter 12, “PCB Materials and Traces,” for guidelines on stackup and
characteristic trace impedance design.
While there are several transitions in each channel, most or all transitions can be designed
for the least negative impact on performance. Because standard non-optimized PCB
structures tend to be capacitive at gigahertz frequencies, a convenient figure of merit for
transitions is excess capacitance. An ideal transition does not have excess capacitance or
inductance.
For each typical transition, techniques to limit excess capacitance and excess inductance
are provided to build a robust channel on the first pass. These design rules, techniques,
and examples are presented in Chapter 13, “Design of Transitions.” The goal is to ensure
tight control of any impedance variation along the entire channel.
In general, minimizing the number of components and layer changes in the high-speed
serial PCB traces brings about the most benefit. Careful design of the traces, vias, and even
connector pads is required for gigahertz speeds.
Powering Transceivers
Supplying noise-free power to the transceivers is a critical factor in achieving low link
error rates and reliable system level operation. This section discusses general principles
that should be applied to transceiver power supply designs.
Linear regulators are required for directly sourcing the power supplies. Although
switching regulators are an attractive option in applications requiring high-power
efficiency, they are unsuitable for directly sourcing transceivers because they can
introduce switching noise, even if care is taken to eliminate the noise.
Power Distribution Architecture
In most system-level designs, multiple voltage levels are required for powering devices on
the board. The supplies for devices that use leading-edge process technologies are
typically low voltages in the region of 1V. At these low voltages, it is important that noise
levels on these supplies be kept at a minimum.
For this reason, Xilinx recommends the use of point-of-load (POL) power distribution
techniques. The POL approach places the power supplies right at the device being
powered, hence the name. Background information on this approach can found in
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=al_point_of_load
.
This approach can be extended to the use of separate linear regulators for groups of
transceivers. This has several advantages including:
• Increased system reliability by eliminating a single point of failure.
• The ability to independently adjust supply voltages for transceiver groups to support
the requirements of different link interfaces.
• Reduction of power requirements from each regulator, which reduces the physical
size, simplifies board layout, and eliminates board hot spots.
Figure 11-2 shows how POL power distribution can be applied to powering transceivers.

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English