Xilinx Virtex-5 RocketIO GTP User Manual

282 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
Table D-2: DRP Address by Attribute
Attribute
Bit
0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AC_CAP_DIS_0
49<14>
AC_CAP_DIS_1
6<1>
ALIGN_COMMA_WORD_0
2b<12>
ALIGN_COMMA_WORD_1
24<3>
CHAN_BOND_1_MAX_SKEW_0
2c<0>
2b<15> 2b<14> 2b<13>
CHAN_BOND_1_MAX_SKEW_1
23<15>
24<0> 24<1> 24<2>
CHAN_BOND_2_MAX_SKEW_0
2c<4> 2c<3> 2c<2> 2c<1>
CHAN_BOND_2_MAX_SKEW_1
23<11>
23<12> 23<13> 23<14>
CHAN_BOND_LEVEL_0
2c<7> 2c<6> 2c<5>
CHAN_BOND_LEVEL_1
23<8> 23<9>
23<10>
CHAN_BOND_MODE_0
2c<9> 2c<8>
CHAN_BOND_MODE_1
23<6> 23<7>
CHAN_BOND_SEQ_1_1_0
2d<3> 2d<2> 2d<1> 2d<0>
2c<15> 2c<14> 2c<13> 2c<12>
2c<11>
2c<10>

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English