Xilinx Virtex-5 RocketIO GTP User Manual

300 www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Appendix D: DRP Address Map of the GTP_DUAL Tile
R
Table D-6: DRP Addresses 18 through 1F
Bit
Address
18 19 1A 1B 1C 1D 1E 1F
0
CLK_COR_
SEQ_1_1_1[7]
CLK_COR_
SEQ_1_2_1[1]
CLK_COR_
SEQ_1_4_1[5]
CLK_COR_
SEQ_2_1_1[3]
CLK_COR_
SEQ_2_3_1[7]
CLK_COR_
SEQ_2_4_1[1]
COMMA_
10B_ENABLE
_1[4]
MCOMMA_
10B_VALUE_
1[2]
1
CLK_COR_
SEQ_1_1_1[6]
CLK_COR_
SEQ_1_2_1[0]
CLK_COR_
SEQ_1_4_1[4]
CLK_COR_
SEQ_2_1_1[2]
CLK_COR_
SEQ_2_3_1[6]
CLK_COR_
SEQ_2_4_1[0]
COMMA_
10B_ENABLE
_1[3]
MCOMMA_
10B_VALUE_
1[1]
2
CLK_COR_
SEQ_1_1_1[5]
CLK_COR_
SEQ_1_3_1[9]
CLK_COR_
SEQ_1_4_1[3]
CLK_COR_
SEQ_2_1_1[1]
CLK_COR_
SEQ_2_3_1[5]
CLK_COR_
SEQ_2_
ENABLE_1[4]
COMMA_
10B_
ENABLE_1[2]
MCOMMA_
10B_VALUE_
1[0]
3
CLK_COR_
SEQ_1_1_1[4]
CLK_COR_
SEQ_1_3_1[8]
CLK_COR_
SEQ_1_4_1[2]
CLK_COR_
SEQ_2_1_1[0]
CLK_COR_
SEQ_2_3_1[4]
CLK_COR_
SEQ_2_
ENABLE_1[3]
COMMA_
10B_
ENABLE_1[1]
MCOMMA_
DETECT_1
4
CLK_COR_
SEQ_1_1_1[3]
CLK_COR_
SEQ_1_3_1[7]
CLK_COR_
SEQ_1_4_1[1]
CLK_COR_
SEQ_2_2_1[9]
CLK_COR_
SEQ_2_3_1[3]
CLK_COR_
SEQ_2_
ENABLE_1[2]
COMMA_
10B_
ENABLE_1[0]
CHAN_
BOND_SEQ_
2_3_1[9]
5
CLK_COR_
SEQ_1_1_1[2]
CLK_COR_
SEQ_1_3_1[6]
CLK_COR_
SEQ_1_4_1[0]
CLK_COR_
SEQ_2_2_1[8]
CLK_COR_
SEQ_2_3_1[2]
CLK_COR_
SEQ_2_
ENABLE_1[1]
COMMA_
DOUBLE_1
CHAN_
BOND_SEQ_
2_2_1[0]
6
CLK_COR_
SEQ_1_1_1[1]
CLK_COR_
SEQ_1_3_1[5]
CLK_COR_
SEQ_1_
ENABLE_1[4]
CLK_COR_
SEQ_2_2_1[7]
CLK_COR_
SEQ_2_3_1[1]
CLK_COR_
SEQ_2_USE_1
DEC_
MCOMMA_
DETECT_1
CHAN_
BOND_SEQ_
2_2_1[1]
7
CLK_COR_
SEQ_1_1_1[0]
CLK_COR_
SEQ_1_3_1[4]
CLK_COR_
SEQ_1_
ENABLE_1[3]
CLK_COR_
SEQ_2_2_1[6]
CLK_COR_
SEQ_2_3_1[0]
COM_BURST
_VAL_1[3]
DEC_
PCOMMA_
DETECT_1
CHAN_
BOND_SEQ_
2_2_1[2]
8
CLK_COR_
SEQ_1_2_1[9]
CLK_COR_
SEQ_1_3_1[3]
CLK_COR_
SEQ_1_
ENABLE_1[2]
CLK_COR_
SEQ_2_2_1[5]
CLK_COR_
SEQ_2_4_1[9]
COM_BURST
_VAL_1[2]
DEC_
VA LI D_
COMMA_
ONLY_1
CHAN_
BOND_SEQ_
2_2_1[3]
9
CLK_COR_
SEQ_1_2_1[8]
CLK_COR_
SEQ_1_3_1[2]
CLK_COR_
SEQ_1_
ENABLE_1[1]
CLK_COR_
SEQ_2_2_1[4]
CLK_COR_
SEQ_2_4_1[8]
COM_BURST
_VAL_1[1]
MCOMMA_
10B_VALUE_
1[9]
CHAN_
BOND_SEQ_
2_2_1[4]
10
CLK_COR_
SEQ_1_2_1[7]
CLK_COR_
SEQ_1_3_1[1]
CLK_COR_
SEQ_2_1_1[9]
CLK_COR_
SEQ_2_2_1[3]
CLK_COR_
SEQ_2_4_1[7]
COM_BURST
_VAL_1[0]
MCOMMA_
10B_VALUE_
1[8]
CHAN_
BOND_SEQ_
2_2_1[5]
11
CLK_COR_
SEQ_1_2_1[6]
CLK_COR_
SEQ_1_3_1[0]
CLK_COR_
SEQ_2_1_1[8]
CLK_COR_
SEQ_2_2_1[2]
CLK_COR_
SEQ_2_4_1[6]
COMMA_
10B_
ENABLE_1[9]
MCOMMA_
10B_VALUE_
1[7]
CHAN_
BOND_SEQ_
2_2_1[6]
12
CLK_COR_
SEQ_1_2_1[5]
CLK_COR_
SEQ_1_4_1[9]
CLK_COR_
SEQ_2_1_1[7]
CLK_COR_
SEQ_2_2_1[1]
CLK_COR_
SEQ_2_4_1[5]
COMMA_
10B_
ENABLE_1[8]
MCOMMA_
10B_VALUE_
1[6]
CHAN_
BOND_SEQ_
2_2_1[7]
13
CLK_COR_
SEQ_1_2_1[4]
CLK_COR_
SEQ_1_4_1[8]
CLK_COR_
SEQ_2_1_1[6]
CLK_COR_
SEQ_2_2_1[0]
CLK_COR_
SEQ_2_4_1[4]
COMMA_
10B_
ENABLE_1[7]
MCOMMA_
10B_VALUE_
1[5]
Do Not
Modify
14
CLK_COR_
SEQ_1_2_1[3]
CLK_COR_
SEQ_1_4_1[7]
CLK_COR_
SEQ_2_1_1[5]
CLK_COR_
SEQ_2_3_1[9]
CLK_COR_
SEQ_2_4_1[3]
COMMA_
10B_
ENABLE_1[6]
MCOMMA_
10B_VALUE_
1[4]
CHAN_
BOND_SEQ_
2_2_1[8]
15
CLK_COR_
SEQ_1_2_1[2]
CLK_COR_
SEQ_1_4_1[6]
CLK_COR_
SEQ_2_1_1[4]
CLK_COR_
SEQ_2_3_1[8]
CLK_COR_
SEQ_2_4_1[2]
COMMA_
10B_ENABLE
_1[5]
MCOMMA_
10B_VALUE_
1[3]
CHAN_
BOND_SEQ_
2_2_1[9]

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English