Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 305
UG196 (v1.3) May 25, 2007
DRP Address by Bit Location
R
4
CLK_COR_
REPEAT_WAIT
_0[2]
CLK_COR_
MAX_LAT_
0[5]
OOBDETECT_
THRESHOLD
_0[1]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[7]
TRANS_
TIME_NON_
P2_0[7]
TRANS_
TIME_FROM
_P2_0[7]
SATA_MIN_
INIT_0[0]
5
CLK_COR_
REPEAT_WAIT
_0[3]
CLK_COR_
KEEP_IDLE_
0
OOBDETECT_
THRESHOLD
_0[2]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[8]
TRANS_
TIME_NON_
P2_0[8]
TRANS_
TIME_FROM
_P2_0[8]
SATA_MIN_
INIT_0[1]
6
CLK_COR_
REPEAT_WAIT
_0[4]
CLK_COR_
INSERT_
IDLE_FLAG_
0
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[9]
TRANS_
TIME_NON_
P2_0[9]
TRANS_
TIME_FROM
_P2_0[9]
SATA_MIN_
INIT_0[2]
7
CLK_
CORRECT_
USE_0
CLK_COR_
DET_LEN_
0[0]
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[10]
TRANS_
TIME_NON_
P2_0[10]
TRANS_
TIME_FROM
_P2_0[10]
SATA_MIN_
INIT_0[3]
8
CLK_COR_
PRECEDENCE_
0
CLK_COR_
DET_LEN_
0[1]
TX_XCLK_
SEL_0
Do Not
Modify
TRANS_
TIME_TO_P2
_0[11]
TRANS_
TIME_NON_
P2_0[11]
TRANS_
TIME_FROM
_P2_0[11]
SATA_MIN_
INIT_0[4]
9
CLK_COR_
MIN_LAT_
0[0]
CLK_COR_
ADJ_LEN_
0[0]
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[12]
TRANS_
TIME_NON_
P2_0[12]
TRANS_
TIME_FROM
_P2_0[12]
SATA_MIN_
INIT_0[5]
10
CLK_COR_
MIN_LAT_
0[1]
CLK_COR_
ADJ_LEN_0[1
]
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[13]
TRANS_
TIME_NON_
P2_0[13]
TRANS_
TIME_FROM
_P2_0[13]
SATA_MIN_
BURST_0[0]
11
CLK_COR_
MIN_LAT_
0[2]
CHAN_
BOND_SEQ_
LEN_0[0]
Do Not
Modify
Do Not
Modify
TRANS_
TIME_TO_P2
_0[14]
TRANS_
TIME_NON_
P2_0[14]
TRANS_
TIME_FROM
_P2_0[14]
SATA_MIN_
BURST_0[1]
12
CLK_COR_
MIN_LAT_
0[3]
CHAN_
BOND_SEQ_
LEN_0[1]
Do Not
Modify
TX_BUFFER_
USE_0
TRANS_
TIME_TO_P2
_0[15]
TRANS_
TIME_NON_
P2_0[15]
TRANS_
TIME_FROM
_P2_0[15]
SATA_MIN_
BURST_0[2]
13
CLK_COR_
MIN_LAT_
0[4]
CHAN_
BOND_SEQ_
2_USE_0
Do Not
Modify
TRANS_
TIME_TO_P2
_0[0]
TRANS_
TIME_NON_
P2_0[0]
TRANS_
TIME_FROM
_P2_0[0]
Do Not
Modify
SATA_MIN_
BURST_0[3]
14
CLK_COR_
MIN_LAT_
0[5]
CHAN_
BOND_SEQ_
2_ENABLE_
0[1]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[1]
TRANS_
TIME_NON_
P2_0[1]
TRANS_
TIME_FROM
_P2_0[1]
SATA_MIN_
WAKE_0[0]
SATA_MIN_
BURST_0[4]
15
CLK_COR_
MAX_LAT_
0[0]
CHAN_
BOND_SEQ_
2_ENABLE_
0[2]
Do Not
Modify
TRANS_
TIME_TO_P2
_0[2]
TRANS_
TIME_NON_
P2_0[2]
TRANS_
TIME_FROM
_P2_0[2]
SATA_MIN_
WAKE_0[1]
SATA_MIN_
BURST_0[5]
Table D-10: DRP Addresses 38 through 3F (Continued)
Bit
Address
38 39 3A 3B 3C 3D 3E 3F

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English