Xilinx Virtex UltraScale+ FPGAs User Manual

Table 75: DRP Map of GTM_DUAL Primitive (cont'd)
DRP
Addres
s
DRP
Bits
R/W Attribute Name Attribute Bits
Attribute
Encoding
DRP
Encoding
0x065 [15:0] R/W CH0_RX_CAL_CFG2B [15:0] 0–65535 0–65535
0x067 [15:0] R/W CH0_RX_CAL_CFG0A [15:0] 0–65535 0–65535
0x068 [15:0] R/W CH0_RX_CAL_CFG0B [15:0] 0–65535 0–65535
0x069 [15:0] R/W CH0_RX_CAL_CFG1A [15:0] 0–65535 0–65535
0x06a [15:0] R/W CH0_RX_CAL_CFG1B [15:0] 0–65535 0–65535
0x06b [15:0] R/W CH0_RX_ADC_CFG0 [15:0] 0–65535 0–65535
0x06c [15:0] R/W CH0_RX_ADC_CFG1 [15:0] 0–65535 0–65535
0x06e [15:0] R/W CH0_RX_CLKGN_CFG0 [15:0] 0–65535 0–65535
0x06f [15:0] R/W CH0_RX_CTLE_CFG0 [15:0] 0–65535 0–65535
0x070 [15:0] R/W CH0_RX_CTLE_CFG1 [15:0] 0–65535 0–65535
0x071 [15:0] R/W CH0_RX_CTLE_CFG2 [15:0] 0–65535 0–65535
0x072 [15:0] R/W CH0_RX_CTLE_CFG3 [15:0] 0–65535 0–65535
0x080 [15:0] R/W CH0_RX_PCS_CFG0 [15:0] 0–65535 0–65535
0x081 [15:0] R/W CH0_RX_PCS_CFG1 [15:0] 0–65535 0–65535
0x082 [15:0] R/W CH0_RX_MON_CFG [15:0] 0–65535 0–65535
0x083 [15:0] R/W CH0_TX_PCS_CFG0 [15:0] 0–65535 0–65535
0x084 [15:0] R/W CH0_TX_PCS_CFG1 [15:0] 0–65535 0–65535
0x085 [15:0] R/W CH0_TX_PCS_CFG2 [15:0] 0–65535 0–65535
0x086 [15:0] R/W CH0_TX_PCS_CFG3 [15:0] 0–65535 0–65535
0x087 [15:0] R/W CH0_TX_PCS_CFG4 [15:0] 0–65535 0–65535
0x088 [15:0] R/W CH0_TX_PCS_CFG5 [15:0] 0–65535 0–65535
0x089 [15:0] R/W CH0_TX_PCS_CFG6 [15:0] 0–65535 0–65535
0x08a [15:0] R/W CH0_TX_PCS_CFG7 [15:0] 0–65535 0–65535
0x08b [15:0] R/W CH0_TX_PCS_CFG8 [15:0] 0–65535 0–65535
0x08c [15:0] R/W CH0_TX_PCS_CFG9 [15:0] 0–65535 0–65535
0x08d [15:0] R/W CH0_TX_PCS_CFG10 [15:0] 0–65535 0–65535
0x08e [15:0] R/W CH0_TX_PCS_CFG11 [15:0] 0–65535 0–65535
0x08f [15:0] R/W CH0_TX_PCS_CFG12 [15:0] 0–65535 0–65535
0x090 [15:0] R/W CH0_TX_PCS_CFG13 [15:0] 0–65535 0–65535
0x091 [15:0] R/W CH0_TX_PCS_CFG14 [15:0] 0–65535 0–65535
0x092 [15:0] R/W CH0_TX_PCS_CFG15 [15:0] 0–65535 0–65535
0x093 [15:0] R/W CH0_TX_PCS_CFG16 [15:0] 0–65535 0–65535
0x094 [15:0] R/W CH0_TX_PCS_CFG17 [15:0] 0–65535 0–65535
0x095 [15:0] R/W CH0_A_CH_CFG0 [15:0] 0–65535 0–65535
0x096 [15:0] R/W CH0_A_CH_CFG1 [15:0] 0–65535 0–65535
0x097 [15:0] R/W CH0_A_CH_CFG2 [15:0] 0–65535 0–65535
0x098 [15:0] R/W CH0_A_CH_CFG3 [15:0] 0–65535 0–65535
Appendix A: DRP Address Map of the GTM Transceiver in UltraScale+ FGPAs
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 136
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English