Xilinx Virtex UltraScale+ FPGAs User Manual

From an architecture perspecve, a Dual contains a grouping of two GTM channels inside one
GTM_DUAL primive, one dedicated external reference clock pin pair, and dedicated reference
clock roung. The reference clock for a GTM_DUAL primive must also be instanated. For duals
operang at line rates lower than 16.3725 Gb/s (NRZ) and 32.7 Gb/s (PAM4), the reference clock
for a Dual can also be sourced from the Dual above via GTNORTHREFCLK or from the Dual
below via GTSOUTHREFCLK. For devices that support stacked silicon interconnect (SSI)
technology, the reference clock sharing via the GTNORTHREFCLK and GTSOUTHREFCLK ports
is limited within its own super logic region (SLR). Duals operang at line rates above
16.3725 Gb/s (NRZ) and 32.7 Gb/s (PAM4) should not source a reference clock from another
Dual.
See the UltraScale device data sheets (see hp://www.xilinx.com/documentaon) for more
informaon about SSI technology.
Reference clock features include:
• Clock roung for northbound and southbound clocks.
• Flexible clock inputs available for the LCPLL.
• Stac or dynamic selecon of the reference clock for the LCPLL.
The Dual architecture has two GTM transceivers, one dedicated reference clock pin pair, and
dedicated north and south reference clock roung. Each GTM dual has three clock pair inputs
available:
• One local reference clock pin pair, GTREFCLK.
• One reference clock pin pair for the Dual above, GTSOUTHREFCLK.
• One reference clock pin pair from the Dual below, GTNORTHREFCLK.
The gure below shows the detailed view of a reference clock mulplexer structure within a
single GTM_DUAL primive. The PLLREFCLKSEL port is required when mulple reference clock
sources are connected to this mulplexer. A single reference clock is most commonly used. In the
case of a single reference clock, connect the reference clock to the GTREFCLK ports and e the
PLLREFCLKSEL ports to 3’b001. The Xilinx soware tools handle the complexity of the
mulplexers and associated roung.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 15
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English