Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 6: LCPLL Reference Clock Selection Multiplexer
LCPLL
0
1
2
3
4
5
6
7
GTREFCLK
GTNORTHREFCLK
LCPLL Output CLK
GTM_DUAL
PLLREFCLKSEL
GTSOUTHREFCLK
GTGREFCLK2PLL
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Single External Reference Clock Use Model
Each Dual has one set of dedicated dierenal reference clock input pins (MGTREFCLK[P/N])
that can be connected to the external clock sources. In a single external reference clock use
model, an IBUFDS_GTM must be instanated to use the dedicated dierenal reference clock
source. The following gure shows a single external reference clock connected to the LCPLL
inside the Dual. The user design connects the IBUFDS_GTM output (O) to the GTREFCLK ports
of GTM_DUAL.
Figure 7: Single External Reference Clock in a Dual
GTM_DUAL
GTREFCLK
MGTREFCLKP
MGTREFCLKN
I
IB
IBUFDS_GTM
O
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Note: The IBUFDS_GTM diagram in the above gure is a simplicaon. The output port ODIV2 is le
oang, and the input port CEB is set to logic 0.
The following gure shows a single external reference clock with mulple Duals connected. The
user design connects the IBUFDS_GTM output (O) to the GTREFCLK ports of the GTM_DUAL
primives. In this case, the Xilinx implementaon tools make the necessary adjustments to the
north/south roung as well as the pin swapping necessary to route the reference clock from one
Dual to another when required.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 16
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English