Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 11: GTM Transceiver Initialization Overview
After Configuration
LCPLL Reset
TX Initialization by
GTTXRESET
RX Initialization by
GTRXRESET
RXRESETDONETXRESETDONE
X20903-052818
The GTM transceiver TX and RX use a state machine to control the inializaon process. They
are paroned into a few reset regions. The paron allows the reset state machine to control
the reset process in a sequence that the PMA can be reset rst and the PCS can be reset aer
the asseron of the TXUSERRDY or RXUSERRDY. It also allows the PMA, the PCS, and
funconal blocks inside them to be reset individually when needed during normal operaon.
The GTM transceiver oers two types of reset: inializaon and component.
• Inializaon Reset: This reset is used for complete GTM transceiver inializaon. It must be
used aer device power-up and conguraon. During normal operaon, when necessary,
GTTXRESET and GTRXRESET can also be used to reinialize the GTM transceiver TX and RX.
GTTXRESET is the inializaon reset port for the GTM transceiver TX. GTRXRESET is the
inializaon reset port for the GTM transceiver RX. During inializaon reset,
TXRESETMODE and RXRESETMODE should be set to sequenal mode. All TX PMA, TX PCS,
RX PMA, and RX PCS component resets should be enabled by seng all required component
bits of TXPMARESETMASK, TXPCSRESETMASK, RXPMARESETMASK, and
RXPCSRESETMASK to High.
• Component Reset: This reset is used for special cases and specic subsecon resets while the
GTM transceiver is in normal operaon. The component that is required to be reset is selected
by seng the associated bit within TXPMARESETMASK, TXPCSRESETMASK,
RXPMARESETMASK, or RXPCSRESETMASK to High. A TX component reset is triggered by
toggling the GTTXRESET port. An RX component reset is triggered by toggling the
GTRXRESET port. Separate component reset ports are available. For the TX, these are
TXCKALRESET, TXFECRESET, TXPCSRESET, and TXPMARESET. For the RX, these are
RXADAPTRESET, RXADCCLKGENRESET, RXBUFRESET, RXCDRFRRESET, RXCDRPHRESET,
RXDFERESET, RXDSPRESET, RXEYESCANRESET, RXFECRESET, RXPCSRESET,
RXPMARESET, and RXPRBSCSCNTRST.
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 24
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English