Xilinx Virtex UltraScale+ FPGAs User Manual

All reset ports described in this secon iniate the internal reset state machine when driven
High. The internal reset state machines are held in the reset state unl these same reset ports are
driven Low. These resets are all asynchronous. The guideline for the pulse width of these
asynchronous resets is one period of the reference clock, unless otherwise noted.
Note: Do not use reset ports for the purpose of power down. For details on proper power-down usage,
refer to Power Down.
Resetting Multiple Lanes and Quads
Reseng mulple lanes in a Dual or mulple Duals aects the power supply regulaon circuit.
Reset Modes
The GTM transceiver TX and RX resets can operate in two dierent modes: sequenal mode and
single mode.
• Sequenal mode: The reset state machine starts with an inializaon or component reset
input driven High and proceeds through all states aer the requested reset states in the reset
state machine, as shown in Figure 13 for the GTM transceiver TX or Figure 18 for the GTM
transceiver RX unl compleon. The compleon of sequenal mode reset ow is signaled
when (TX/RX)RESETDONE transions from Low to High.
• Single mode: The reset state machine only executes the requested component reset
independently for a predetermined me set by its aribute. It does not process any state aer
the requested state, as shown in Figure 13 for the GTM transceiver TX or Figure 18 for the
GTM transceiver RX. The requested reset can be any component reset to reset the PMA, the
PCS, or funconal blocks inside them. The compleon of a single mode reset is signaled when
(TX/RX)RESETDONE transions from Low to High.
The GTM transceiver inializaon reset must use sequenal mode. All component resets can be
operated in either sequenal mode or single mode. The GTM transceiver uses (TX/
RX)RESETMODE to select between sequenal reset mode and single reset mode. The following
table provides conguraon details that apply to both the GTM transceiver TX and GTM
transceiver RX. Reset modes have no impact on LCPLL reset. During normal operaon, the GTM
transceiver TX or GTM transceiver RX can be reset by applicaons in either sequenal mode or
single mode (GTM transceiver RX only), which provides exibility to reset a poron of the GTM
transceiver. When using either sequenal mode or single mode, (TX/RX)RESETMODE must be
set to the desired value of 50 ns before the asserons of any reset.
Table 11:
GTM Transceiver Reset Modes Operation
Operation Mode (TX/RX)RESETMODE
Sequential Mode
2'b00
Single Mode
2'b11
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 25
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English