Xilinx Virtex UltraScale+ FPGAs User Manual

TX Initialization and Reset
The GTM transceiver TX uses a reset state machine to control the reset process. The GTM
transceiver TX is paroned into two reset regions, TX PMA and TX PCS. The paron allows TX
inializaon and reset to be operated only in sequenal mode, as shown in the gure below.
The inializing TX must use GTTXRESET in sequenal mode. Acvang the GTTXRESET input
can automacally trigger a full asynchronous TX reset. The reset state machine executes the
reset sequence, as shown in the gure below, covering the whole TX PMA and TX PCS. During
normal operaon, when needed, sequenal mode allows you to reset the TX from acvang
TXPMARESET and connue the reset state machine unl TXRESETDONE transions from Low
to High.
The TX reset state machine does not reset the PCS unl TXUSERRDY is detected High. Drive
TXUSERRDY High aer all clocks used by the applicaon including TXUSRCLK are shown as
stable.
Figure 13: GTM Transceiver TX Reset State Machine Sequence
Wait until
GTTXRESET from
High to Low
GTTXRESET
High
TX CKCAL Reset
TXPMARESETMASK[0]
= 1?
TXPMARESETMASK[1]
= 1?
TX PMA Top Reset
Yes
No
TXPCSRESETMASK[0]
= 1?
TX FEC Reset
Yes
No
TXPCSRESETMASK[1]
= 1?
TX PCS Top Reset
TXRESETDONE High
Yes
Yes
No
No
Wait for TXUSERRDY
= 1
X20905-060518
Chapter 2: Shared Features
UG581 (v1.0) January 4, 2019 www.xilinx.com
Virtex UltraScale+ GTM Transceivers 27
Send Feedback

Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English