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Chapter 6: Solving Problems
Solving Target System Problems
• Restore the SRR0, SRR1, DAR, DSISR registers.
• Issue an RFI (Return from Interrupt) instruction.
Upon entering the ISR, the processor clears the MSR.RI bit, and copies
the IP (Instruction Pointer)->SRR0 and the MSR->SRR1. The SRR0
and SRR1 are the save and restore registers. These contain the
information needed to return to the state prior to the interrupt.
The RI bit will prevent the processor from breaking into debug mode
with a maskable debug port breakpoint. A non-maskable breakpoint is
required to break the processor when the RI bit is cleared, resulting in
a possible non-recoverable state.
Software breakpoints place a “Trap” instruction into the breakpoint
address. If the trap instruction is executed within an ISR, a break to
background mode will occur. This causes the SRR0 and SRR1 registers
to be written over, causing a non-recoverable state. If the exception
handler saves these registers, and sets the MSR.RI bit, the software
breakpoint will always be recoverable.
If hardware breakpoints have no effect
Hardware breakpoints by default will not break the processor if they
are set within an exception handler which has not saved the SRR’s and
set the MSR.RI bit. However, these can quite easily be reprogrammed
to assert a non-maskable break. Note that the breakpoint will halt the
processor, but will cause a non-recoverable state.
To reprogram the hardware breakpoint to assert a non-maskable break:
M>bc -e hwbp
M>reg lctrl2
reg lctrl2=02018000
M>reg lctrl2=02018800 # OR in 0x00000800 with previous value
Hardware breakpoints will now cause a non-maskable break, which will
halt the processor regardless of the status of the MSR.RI bit. Again,
note that in this case the break will be non-recoverable if the exception
handler has not saved the SRR’s.
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