Intel
®
Server Board S2600CP and Server System P4000CP TPS Intel
®
Server System P4000CP Power System Options
Revision 1.1
Intel order number G26942-003
157
13.4.2.10 DC/DC Converters Dynamic Loading
The output voltages remains within limits specified in table above for the step loading and
capacitive loading specified in the table below. The load transient repetition rate is only a test
specification. The step load may occur anywhere within the MIN load to the MAX load shown
in Tables 143 and 144.
Table 127. Transient Load Requirements
Output Max Step Load Size Max Load Slew Rate Test capacitive Load
+ 3.3VDC
5A
0.25 A/
s 250 F
+ 5VDC
5A
0.25 A/
s 400 F
+5Vsb
0.5A
0.25A/
s 20 F
13.4.2.11 DC/DC Converter Capacitive Loading
The DC/DC converters is stable and meet all requirements with the following capacitive loading
ranges. Minimum capacitive loading applies to static load only.
Table 128. Capacitive Loading Conditions
Converter output Min Max Units
+3.3VDC 250 6800
F
+5VDC 400 4700
F
5Vstby 20 350
F
13.4.2.12 DC/DC Converters Closed Loop stability
Each DC/DC converter is unconditionally stable under all line/load/transient load conditions
including capacitive load ranges specified in Section 13.5.2.11. A minimum of: 45 degrees
phase margin and -10dB-gain margin is required. The PDB provides proof of the unit’s
closed-loop stability with local sensing through the submission of Bode plots. Closed-loop
stability must be ensured at the maximum and minimum loads as applicable.
13.4.2.13 Common Mode Noise
The Common Mode noise on any output does not exceed 350mV pk-pk over the frequency
band of 10Hz to 20MHz.
The measurement shall be made across a 100Ω resistor between each of DC outputs,
including ground, at the DC power connector and chassis ground (power subsystem
enclosure).
The test set-up shall use a FET probe such as Tektronix model P6046 or equivalent.
13.4.2.14 Ripple/Noise
The maximum allowed ripple/noise output of each DC/DC Converter is defined in below Table
95. This is measured over a bandwidth of 0Hz to 20MHz at the PDB output connectors. A 10F
tantalum capacitor in parallel with a 0.1F ceramic capacitor are placed at the point of
measurement.