TS-990S
7
Fig. 3 Frequency confi guration of the transmission and sub receiver blocks
CIRCUIT DESCRIPTION
AD9835
DDS
ADF4001
PLL
PLL
ADF4001
FMOD
R40M
VCO
40MHz
FM IC
455kHz
3rd IF
AF
ADC
/DAC
DSP
AF OUT
1st IF
2nd IF
1st IF
DDS
AD9951
PLL
ADF4111
VCO
x2
x2
x2
TX
MIX
RX
MIX
RX
MIX
IFA
IFB
AD9835
DDS
RX
MIX
TX
MIX
FM
24kHz
24kHz
10.695MHz
73.095MHz
11.374MHz
SUB RX IFB (To Scope unit)
SUB RX IFA/TX (To Scope unit)
MIC IN
except FM
TX/RX
MIX
15.6MHz
ANT
2-2. Reference Signal Generator
The frequency of the voltage-controlled crystal oscillator
(VCXO: X1 and Q13) is locked to 15.6MHz and used as a
reference frequency for the transmission and sub receiver
blocks. The 15.6MHz signal is applied to pin 5 of the PLL (IC1)
via the buffer (Q19) and amplifi er (Q2). The signal which is
applied to pin 5 is divided by N, and the 40MHz reference
signal which is applied to pin 8 is divided by R. These sig-
nals are phase-compared to lock the VCXO frequency at
15.6MHz. The phase-locked 15.6MHz is frequency-doubled
by the multiplier (Q34) to generate 31.2MHz.
The 31.2MHz is used as a reference signal for the DDS
(IC12) for the 3rd local oscillator (SLO3) and the DDS (IC11)
for transmission 1st local oscillator (TLO1). The 31.2MHz is
frequency-doubled by the multiplier (Q50 and Q52) to gener-
ate 62.4MHz, and is used as a reference signal for the PLL
(IC10) that generates a reference signal for the receiver’s 1st
local oscillator (SLO1).
2-3. TLO1/SLO1/SLO2/SLO3
■
TLO1 (1st Local Oscillator for Transmission)
The DDS (IC11) outputs a frequency ranging from 8.33 to
8.47MHz in reference to the 31.2MHz. It passes through the
ceramic fi lter (CF1) and is applied to the PLL (IC16). The 8.33
to 8.47MHz is divided by R by the PLL (IC16) and is used for
a phase comparison frequency (fø).
The VCO (Q17, Q18, Q39, and Q40) of TLO1 oscillates
at frequencies ranging from 73.125 to 133.125MHz. It is ap-
plied to pin 5 of the PLL (IC16) and is divided by N inside the
PLL.
The phase comparator inside the PLL compares the
phase between fø and the frequency divided by N, and
generates the phase-locked oscillation signal for the TL01.
The output signal from the VCO (Q17, Q18, Q39, and Q40)
is amplifi ed by Q56, passes through the BPF, ATT and LPF,
and is sent as the TLO1 (73.1 to 133.1MHz).
■
SLO1 (1st Local Oscillator for Sub Receiver)
The VCO (Q16) oscillates at 393.6MHz. It is applied to
pin 5 of the PLL (IC10) via the BPF, and the 62.4MHz which
is obtained by multiplying the 15.6MHz reference frequency
by 4 is applied to pin 8. The signal input to pin 5 is divided
by N and input to pin 8 is divided by R. They are phase-
compared to phase-lock the frequency, which is used as a
reference of DDS (IC14).
The DDS outputs the 13.17 to 32.88MHz with the IFB
selected. It is amplifi ed by the wide-band amplifi er (IC15),
and output as an SLO1 via the BPF. The DDS outputs the
36.56 to 66.55MHz with the IFA selected, and is amplifi ed
by the wide-band amplifi er (IC15). The output is frequency-
doubled by the multiplier (D19), and is sent as an SLO1 (73.1
to 133.1MHz) via the BPF.
■
SLO2 (2nd Local Oscillator for Sub Receiver)
The SLO2 outputs a 62.4MHz signal which is the
15.6MHz reference frequency multiplied by 4.
The 15.6MHz which is sent from the reference oscillation
is applied to the frequency doubler (Q34) via the buffers (Q19
and Q25), and 31.2MHz is generated. The 31.2MHz is fre-
quency doubled by the multiplier (Q50 and Q52) to generate
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