Pre ss the powe r but ton
The EC ARM receives
the signa l
Startup successful? Ex it, n o s tar tup
N
Y
En able
PWR_BT N_N_PC
The C OME mo dule
receive the signal
The C OME mo dule
t ran smi ts S 3 to trigger
t he star tup flo w
The EC ARM receives
the S3 signal
Th e EC A RM en able s
power main unit power
Po wer-up
1VÃ ...
FPGA (PC Ie d evi ce)
configuration complete
The C OME mo dule
receives PC_P WROK
Control panel power-up
5V 12V
Control panel FPGA
configuration
Control panel PSOC boot
Control panel
init ializati on (white
bac klig ht tur ned o n with
a low brightness)
Control panel ready
No display on the LCD
Disp lay initi alization,
bac klig ht tur ned o ff, no
eDP signal output
No display on the LCD
DSP FPGA output s eDP
data to the LCD
FPGA turns on the LCD
bac klig ht and adjus ts the
brightness
LCD backl ight tur ned no
bu t wi th no d ispl ay
Co rrec t im age (BI OS
st artup sc reen ) di spla yed
on t he LC D
The C OME mo dule
outputs the startup screen
Operating status
indic ator (un der t he
pow er but ton) bl ink s
orange
Operating status
indic ator (pow er but ton)
is steady green
The C OME mo dule
fi ni shes th e BIO S pha se
OS lo ading is c omplete
loading is complete
loading is complete
Start to load the OS, and
the disp lay r esol ution i s
adj u sted
Logo (MINDRAY)
di splaye d on the LC D
The d isplay reso lution is
final ly deter min ed
The OS desktop appears
Desktop image displayed
on t he LC D
No display on the LCD
No display on the LCD
Sta rt Do pple r
Do ppler st artup sc reen
di splaye d on the LC D
Dis k ind icato r bli nks
green
Po wer ed b y ba tte ry-
>battery status indicator,
bl inking gre en
The EC ARM receives
t he CB _RST _N signal
FPGA power-up
D3V3 pow er-up
successfu l
The EC ARM tr ansmits a
PC_PWROK in dicatio n
The COM E module is
pow ered u p an d
t ran smi ts t he C B_RST _N
signal
Exi t, no s tar tup
N
Operating status indicator
(pow er but ton) bl ink s red
and green alternately and
becomes off in 10s
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