92
Remark
For timer and counter present values, there are no limits on index register numbers used.
(c) A case where Indexing has been performed, and the actual process device, would be as follows:
(When Z0 20 and Z1 -5)
Fig. 3.7 Ladder Example and Actual Process Device
(3) Indexing with 32-bit (Universal model QCPU (excluding Q00UJCPU) and LCPU)
A method of specifing index registers in indexing with 32-bit can be selected from the following two methods.
• Specifing the index registers’ range used for indexing with 32-bit.
• Specifing the 32-bit indexing using “ZZ” specification.
32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See the programming tool
operating manual for the available programming tools.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher. (excluding Q00UJCPU)
•QnUDE(H)CPU
• LCPU
Ladder Example Actual Process Device
SM400
Present value of timer
X0
Value set for timer
T0
K100
T0Z4K4Y30
BCD
SM400
Present value of counte
X1
Value set for counter
C100
K10
C100Z6K2Y40
BCD
X0
MOV K20 Z0
MOV K 5 Z1
X1
MOV K2X50Z0 K1M38Z1
Description
Converts K20 into a hexadecimal number.
X1
MOVK2X64
K1M33
K2X50Z0
K1M38Z1
K1M(38 - 5) = K1M33
K2X(50 + 14) = K2X64
X0
MOV K20 Z0
MOV K Z1
X1
MOV D0Z0 K3Y12FZ1
5
D
escription
Hexadecimal numbe
X1
MOV D20
K3Y12A
D
0Z0
K3Y12FZ1
D (0 + 20) = D20
K3Y(12F - 5) = K3Y12A
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