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MULTIJUNCTION TIMERS
10.7 TID (Input-Related 16-Bit Timer)
32180 Group User’s Manual (Rev.1.0)
10.7.6 Outline of Each Mode of TID
Each mode of TID is outlined below. TID modes can be selected from the following, only one at a time.
(1) Fixed period count mode
In fixed period count mode, the timer uses a reload register to generate an interrupt request at intervals of
(reload register set value + 1).
When the timer is enabled (by writing to the enable bit in software) after setting the reload register (initial
value being undefined), the counter is loaded with the content of the reload register and starts counting
synchronously with the count clock. The counter counts down and when it underflows after reaching the
minimum count, the counter is loaded with the content of the reload register and continues counting. To stop
the counter, disable count by writing to the enable bit in software. An interrupt request can be generated each
time the counter underflows.
The (reload register set value + 1) is effective as count value.
Count clock
Counter
H'FFFF
H'0000
Enabled
(by writing to the enable bit)
Underflow
(first time)
TID0 interrupt request
due to underflow
Enable bit
Count down from
the reload register
set value
Note: • This diagram does not show detailed timing information.
Reload register
H'E000
Underflow
(second time)
H'E000
H'(E000-1) H'(E000-1)
H'E000
H'(E000-1)
Count down from
the reload register
set value
Count down from
the reload register
set value
Undefined
value
Figure 10.7.3 Typical Operation in TID Fixed Period Count Mode
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