Renesas M32R/ECU Series User Manual

2
2-5
32180 Group User’s Manual (Rev.1.0)
CPU
2.3.5 Floating-point Status Register: FPSR (CR7)
0000 000 0000000
2 3 4 5 6 7 8 9 10 11 12 13 14 b151b0
00 00000100000000
EV
DN CE CX CU CZ CO CV RM
18 19 20 21 22 23 24 25 26 27 28 29 30 b3117b16
EUEX
FS FX FU FZ
0
FO
0
FV
EZ EO
<After reset: H’0000 0100>
b Bit Name Function R W
0 FS Reflects the logical sum of FU, FZ, FO and FV. R –
Floating-point Exception Summary Bit
1 FX Set to "1" when an inexact exception occurs (if EIT processing is R W
Inexact Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
2 FU Set to "1" when an underflow exception occurs (if EIT processing is R W
Underflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
3 FZ Set to "1" when a zero divide exception occurs (if EIT processing is R W
Zero Divide Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
4 FO Set to "1" when an overflow exception occurs (if EIT processing is R W
Overflow Exception Flag unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
5 FV Set to "1" when an invalid operation exception occurs (if EIT processing R W
Invalid Operation Exception Flag is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
6–16 No function assigned. Fix to "0". 00
17 EX 0: Mask EIT processing to be executed when an inexact exception occurs. R W
Inexact Exception Enable Bit 1: Execute EIT processing when an inexact exception occurs.
18 EU 0: Mask EIT processing to be executed when an underflow exception R W
Underflow Exception Enable Bit occurs.
1: Execute EIT processing when an underflow exception occurs.
19 EZ 0: Mask EIT processing to be executed when a zero divide exception R W
Zero Divide Exception Enable Bit occurs.
1: Execute EIT processing when a zero divide exception occurs.
20 EO 0: Mask EIT processing to be executed when an overflow exception R W
Overflow Exception Enable Bit occurs.
1: Execute EIT processing when an overflow exception occurs.
21 EV 0: Mask EIT processing to be executed when an invalid operation R W
Invalid Operation Exception Enable Bit exception occurs.
1: Execute EIT processing when an invalid operation exception occurs.
22 No function assigned. Fix to "0". 00
23 DN 0: Handle the denormalized number as a denormalized number. R W
Denormalized Number Zero Flush Bit 1: Handle the denormalized number as zero.
(Note 2)
24 CE 0: No unimplemented operation exception occurred. R
(Note 3)
Unimplemented Operation 1: An unimplemented operation exception occurred. When the bit is
Exception Cause Bit set to "1", the execution of an FPU operation instruction will clear it to "0".
25 CX 0: No inexact exception occurred. R
(Note 3)
Inexact Exception Cause Bit 1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
2.3 Control Registers

Renesas M32R/ECU Series Specifications

General

Brand	Renesas
Model	M32R/ECU Series
Category	Computer Hardware
Language	English