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REAL TIME DEBUGGER (RTD)
14.3 Functional Description of the RTD
32180 Group User’s Manual (Rev.1.0)
14.3 Functional Description of the RTD
14.3.1 Outline of the RTD Operation
Operation of the RTD is specified by a command entered from devices external to the chip. A command is
indicated by bits 16–19 (Note 1) of the RTD received data.
Table 14.3.1 RTD Commands
RTD Received Data Command
b19 b18 b17 b16 Mnemonic RTD Function
0 0 0 0 VER (VERify) Continuous monitor
0100
0101
0 1 1 0 VEI (VErify Interrupt request) RTD interrupt request
0 0 1 0 RDR (ReaD RAM) Real-time RAM content output
0 0 1 1 WRR (WRite RAM) RAM content forcible rewrite (with verify)
1 1 1 1 RCV (ReCoVer) Recover from runaway condition (Note 2), (Note 3)
0 0 0 1 System reserved (use inhibited)
↑ (Note 1)
Note 1: The RTD received data bit 19 actually is not stored in the command register, and except for the RCV
command, handled as a “Don’t care” bit. (Bits 16–18 are effective for the command specified.)
Note 2: The RCV command must always be transmitted twice in succession.
Note 3: For the RCV command, all bits, not just 16–19, (i.e., bits 0–15 and bits 20–31) must be set to "1".
14.3.2 Operation of RDR (Real-time RAM Content Output)
When the RDR (real-time RAM content output) command is issued, the RTD is enabled to transfer the contents
of the internal RAM to external devices without causing the CPU’s internal bus to stop. Because the RTD reads
data from the internal RAM while there are no transfers performed between the CPU and internal RAM, no extra
CPU load is incurred.
Only the 32-bit word-aligned addresses can be specified for read from the internal RAM. (The two low-order
address bits specified by a command are ignored.) Data are read out and transferred from the internal RAM in
32-bit units.
Figure 14.3.1 RDR Command Data Format
31
X 0 0 10
19 18 17
16
0
15
0
14 13 12 1
A16
0
X
20
A17A28A29
Command (RDR) Specified address
Note: • X = Don't care. (However, if issued immediately after the RCV command, bits 20-31 must all be set to 1.)
RTDRXD
(MSB side)
(LSB side)
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