Renesas TPS-1 User Manual

TPS-1 User’s Manual: Hardware 3. Host Interface
R19UH0081ED0107 Rev. 1.07 page 18 of 86
Jul 30, 2018
3.2.2. Signal description of the parallel interface
The shared memory has an address space of 64 Kbyte (refer to chapter “Shared memory structure”). The typical page size is 16 KByte. For a correct
alignment you have to connect the highest address bits to the signals LBU_SEG0_IN and LBU_SEG1_IN (see Table 3-2, Figure 3-2 and Figure 3-3).
LBU
_
Ax_
IN
(13
:
0)
A
(
15
:
0
)
A
(13
:0
)
A(15:14)
Ext
. Host CPU
Figure 3-2: TPS-1 with address page 16 Kbyte
You can also choose a page size of 4 Kbyte. When you choose 4 Kbyte pages you have less space inside the NRT area for configuration slots and
subslots.
LBU
_Ax_IN(15:14)
LBU_Ax_IN(11:0)
A(13:0)
A(11:0)
A(13:12)
Ext. Host CPU
TPS-1
Host Interface
LBU_SEG(1:0)_IN
Figure 3-3: TPS-1 with address page 4 Kbyte
LBU_SEG(1:0)_IN
LBU_Ax_IN(13:12)
TPS-1
Host Interface

Renesas TPS-1 Specifications

General

Brand	Renesas
Model	TPS-1
Category	Controller
Language	English