page 6 of 86
Table of Contents
1. OVERVIEW ............................................................................................................................................................................ 8
1.1. FEATURES ................................................................................................................................................................................. 8
1.2. ABSTRACT ................................................................................................................................................................................. 9
1.3. BLOCK DIAGRAM ..................................................................................................................................................................... 10
2. PIN FUNCTION.................................................................................................................................................................... 11
2.1. SIGNAL OVERVIEW AND DESCRIPTION ..................................................................................................................................... 11
2.2. GPIO MULTIPLEXING .............................................................................................................................................................. 14
2.3. SUPPLY VOLTAGE CIRCUITRY ................................................................................................................................................. 15
2.4. SIGNALS FOR IRT COMMUNICATION ....................................................................................................................................... 16
3. HOST INTERFACE............................................................................................................................................................... 17
3.1. TESTING DPRAM INTERFACE ................................................................................................................................................. 17
3.2. PARALLEL INTERFACE ............................................................................................................................................................ 17
3.2.1. Operating modes of the parallel interface .................................................................................................................... 17
3.2.2. Signal description of the parallel interface .................................................................................................................. 18
3.2.3. Memory Segmentation at 4 kByte and 16 kByte page size .......................................................................................... 20
3.2.4. Connection example for a 8bit data bus ....................................................................................................................... 22
3.2.5. Connection example for a 16-bit data bus .................................................................................................................... 23
3.3. SPI SLAVE INTERFACE ............................................................................................................................................................ 24
3.3.1. Serial access to the shared memory ............................................................................................................................. 25
3.3.2. SPI Slave Interface Timing .......................................................................................................................................... 28
3.3.3. SPI Slave Interface Reset Timing ................................................................................................................................ 33
4. SHARED MEMORY STRUCTURE........................................................................................................................................ 34
4.1. EVENT COMMUNICATION WITH THE TPS-1 FIRMWARE............................................................................................................ 36
4.2. EVENTS FROM THE TPS-1 FIRMWARE TO THE HOST ................................................................................................................ 37
4.3. EVENTS FROM THE HOST TO THE TPS-1 FIRMWARE ................................................................................................................ 38
4.4. INTERRUPT COMMUNICATION WITH THE TPS-1 ...................................................................................................................... 39
4.4.1. How to generate an interrupt by an event ................................................................................................................... 39
5. TPS-1 BOOT SUBSYSTEM ................................................................................................................................................... 43
5.1. HARDWARE STRUCTURE FOR THE BOOT OPERATION............................................................................................................... 43
5.2. LOADING AND UPDATE OF THE FIRMWARE DURING THE MANUFACTURING PROCESS ............................................................... 44
5.2.1. UART interface (UART boot) ........................................................................................................................................ 44
5.2.2. SPI master interface (Boot Flash) ................................................................................................................................ 45
6. IO LOCAL GPIO INTERFACE .............................................................................................................................................. 47
6.1. GPIO (DIGITAL INPUT AND OUTPUT) ....................................................................................................................................... 47
6.2. STATUS LEDS OF THETPS-1 ................................................................................................................................................... 48
6.3. I2C-BUS – LWL DIAGNOSTIC .................................................................................................................................................. 48
7. TPS-1 WATCHDOG .............................................................................................................................................................. 49
7.1. SIGNAL WD_OUT (PIN B12) ................................................................................................................................................... 49
7.2. SIGNAL WD_IN (PIN A11) ....................................................................................................................................................... 50
8. PROFINET IO SWITCH ........................................................................................................................................................ 51
8.1. 100BASE-TX INTERFACE ......................................................................................................................................................... 52
8.1.1. 100Base-TX interface (Port 1) ...................................................................................................................................... 52
8.1.2. 100Base-TX interface (Port 2) ...................................................................................................................................... 52
8.2. 100BASE-FX INTERFACE (FIBER OPTIC) ................................................................................................................................. 52
8.2.1. 100Base-FX interface (Port 1) ...................................................................................................................................... 53
8.2.2. 100Base-FX interface (Port 2) ...................................................................................................................................... 53
8.3. I2C-BUS – LWC DIAGNOSTIC ................................................................................................................................................. 53
8.4. ADDITIONAL TPS-1 PINS ......................................................................................................................................................... 54
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