Renesas TPS-1 User Manual

TPS-1 User’s Manual: Hardware 3. Host Interface
R19UH0081ED0107 Rev. 1.07 page 25 of 86
Jul 30, 2018
3.3.1. Serial access to the shared memory
The access to the shared memory is processed with command bytes that are part of the SPI-Header. The command structure depends on the device.
Generally, an SPI interface works like a shift register. The clock is driven by the SPI master. After processing the SPI command, the SPI slave sends the
requested data to the host CPU (or data is only sent to the SPI slave). As long as the chip select signal is active, data are exchanged between the devices
(master – slave).
3.3.1.1. Header structure
The content and meaning of SPI data is defined by the implementation of the SPI slave. The following chapter describes the structure of the SPI slave
commands.
Table 3-7: SPI header structure
Header Data
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 – max.
Command
Address
Address
Length
Length
1 Byte 1 Byte 1 Byte 1 Byte 1 Byte 1 Byte .. max. length Shared Memory
An indirect command contains the length information in byte 3 and 4. A direct command contains the length information in the bits 0 to 3 of the
command byte. The maximum address access is limited to 15 byte.

Renesas TPS-1 Specifications

General

Brand	Renesas
Model	TPS-1
Category	Controller
Language	English