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8.5.
INTEGRATED VOLTAGE REGULATOR 1.5 V ............................................................................................................................... 54
9. CLOCK CIRCUIT .................................................................................................................................................................. 56
9.1. USING THE INTERNAL CLOCK OSCILLATOR .............................................................................................................................. 56
9.2. EXTERNAL CLOCK SOURCE ...................................................................................................................................................... 57
10. RESET OF THE TPS-1 ..................................................................................................................................................... 58
11. BOUNDARY SCAN INTERFACE (JTAG) ......................................................................................................................... 59
11.1. CIRCUIT RECOMMENDATION OF THE JTAG INTERFACE .......................................................................................................... 60
SETTING OF OPERATING MODES ................................................................................................................ 61
HOST INTERFACE .................................................................................................................................................................... 62
Host Parallel Interface ................................................................................................................................................. 62
Host Serial Interface ..................................................................................................................................................... 63
LOCAL I/O-CONFIGURATION ................................................................................................................................................... 64
IO Parallel ..................................................................................................................................................................... 64
IO Serial Interface ........................................................................................................................................................ 67
IO Local Interface ......................................................................................................................................................... 69
IO Local parallel Interface ............................................................................................................................................ 69
Configuration of the IO Local Parallel Interface.......................................................................................................... 69
Configuration of the IO Local Serial interface (SPI Master) ....................................................................................... 70
I&M0 Configuration (I&M0 data) “Deleted” OK? ................................................................................................ 71
ETHERNET INTERFACE CONFIGURATION ................................................................................................................................ 72
COPYING THE CONFIGURATION DATA INTO THE BOOT FLASH .................................................................................................. 73
GENERATING A COMPLETE SERIAL BOOT FLASH IMAGE........................................................................................................... 74
BOARD DESIGN INFORMATION ................................................................................................................... 75
VOLTAGE SUPPLY .................................................................................................................................................................... 75
SWITCHING REGULATOR ......................................................................................................................................................... 75
Wiring for the Switching Regulator ............................................................................................................................. 76
Layout Example for Switching Regulator .................................................................................................................... 77
BOARD DESIGN RECOMMENDATIONS FOR ETHERNET PHY ..................................................................................................... 78
Supply Voltage Circuitry .............................................................................................................................................. 78
100BASE-TX Mode Circuitry ....................................................................................................................................... 80
Unused 100Base-TX Interface ...................................................................................................................................... 81
100BASE-FX Mode Circuitry ....................................................................................................................................... 82
Unused 100Base-FX interface ...................................................................................................................................... 85
FAST START UP REQUIREMENTS ................................................................................................................ 86