Theory of Operation-AA
501
A dc signal, proportional to the input signal amplitude
appears at pin 4 of
U1221A. The bias voltages on pins 5
and 6 of
U1221A and Bare such that pin 2 of U1221Agoes
low when the input signal is higher than the range the
input stage is presently in. This low appears at pin 10 of
U1031 which causes the binary up-down counter tocount
down. If the input attenuator is intheleast sensitive range,
a high exists on pin 1 of
U1032A. A Iowthen exists on pin3
of
U1032Awhich preventsthe underrange LEDfrom being
illuminated. Pin 1 of
U1221 B is low when the input signal is
lower than the input attenuator range. Pin 6 of
U1032B is
high in the most sensitive range. The up-down counter
counts only when pin 5 is low. This occurs when the input
signal level is higherthantheattenuator
rangeand the unit
is not in the least sensitive position, or when the input
signal is lower than the input attenuator
rangeand theunit
is not in the most sensitive range. The over-range and
underrange LEDs are illuminated through
(21508 and
Q1509 respectively. When the bases of these transistors
are high, through theoutputs of
U1032A and U10328, the
lights are illuminated. The overrange and underrange
lights are also controlled by thedistortion amplifier gain in
the level mode. Theseinputs, from
U1407, areshown at the
bases of transistors
(21509 and (21508.
U1012A decodes the odd 10 dB steps in theinput stage
gain and supplies this information to the distortion
amplifier control and to
U1021 for decimal point and offset
formatting purposes.
Distortion amplifier gain is controlled in a manner
similar to the input circuitry gain.
U1221C, and U1221D
are the level comparator and U1132A. U1132B, and
U1132D perform the enable gating function.
The gain control input for the distortion amplifier is
selected by
U1033, a 4 bit and/or selector. In the level
mode pin 9 is high, pin 14 is low, and pins 6, 4, and 2 are
routed to the outputs. This selects the Input Level Range
Switch,
S1521, as the gain control input. In the distortion
modes, pin 14 is high, 9 is low and pins 7, 5 and 3 are
connected to the output. The distortion range switches
now control the gain.
The signals from and to
U1032C control the switching
of
U1033. A dc voltage proportional to the output of the
distortion amplifier connects to pin 11 of
U1221D. The
operation of
U1221 and U1132 are identical as described
for the input stage
up/down counter. 'These gates control
up/down counter, U1131, for the distortion amplifier gain.
A three to eight decoder driver,
U1124, supplies decimal
output for the distortion amplifier gain control circuitry.
A binary adder,
U1021, shown on schematic 12, sums
.
the gain of the input stage and the distortion amplifier.
Pins
7,
5 3 and
6
provide input stagegain information. Pins
4 and 2 provide distortion amplifier gain information. This
sum is decoded by
U1022, and passes through CR1022,
CR1025 and CR1028. These diodes drive U1012B and
U1111 to operate the pV, mV, and Volts annunicator LEDs.
The control source for the decimal points is selected by
U1013, a 4 bit and/or selector which operates as a
multiplexer. In the volts mode, the decimal points are
controlled by the decoded decimal information from
U1022 and the diodes. In the distortion modes, the
decimal points are controlled by the distortion amplifier
gain. Gain information from the distortion amplifier
appears at pins
1. 3, 5 and 7. In the dB modes, U1013 is
disabled, and
(21106 is turned on by U1112A or U1112B.
This illuminates the proper decimal point for all dB
displays.
A 4 bit and/or selector
(U1123) operating as a
mutliplexer, selects the control source for the dB offset
generator. In the level mode, the offset iscontrolled by the
sum at the output of
Ul021. In thedistortion modes U1123
is controlled by the distortion amplifier gain.
Power Supplies
0
There are three operating voltagesinthe AA 501:
t
and
-
15 V dc and 4-5 V dc. The k15 V supplies the
operational amplifiers, linear circuitry and CMOS, while
+
V is used for the logic and display circuitry.
The
+5 V dc supply is derived from the 4-11.5 V dc
supply in the mainframe. A three terminal votlage
regulator,
U1523, provides +5 V and includes built-in
current limiting. Additional overcurrent protection is
provided by
F1621.
The +15 V dc supply is regulated from the +33 V dc
mainframe supply. The reference voltage, against which
the regulator output, divided down by
Rl425 and R1426 is
compared, is supplied by
VR1401. Errors between the
reference voltage and divided output are amplified by
U1420B and Q1510. The mainframe
NPN
transistor and
Q1513 form a Darlington series-pass transitor. Frequency
compensation for stability is provided by
R1521 and
C1510. Current limiting is accomplished by Q1511 which
senses the voltage across
R1519. When the current
delivered by the
+I5 volt supply exceeds about 500 mA,
Q1511 turns on. This shunts base drive current from
Q1513 lowering the output voltage. Fuse F1610 provides
additional protection.
-15
V
Supply
The -15 V is supplied from the -33 V dc in the
mainframe. Amplifier
U1420A compares the regulated
+15 V supply with the -15 V through
R1420 and R1421.
Voltage differences are amplified by U1420A and Q1520.
Scans
by
ARTEK MEDL4
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