Specifications
Table 1-4: Analog output (cont.)
Characteristics Description
Phase noise without jitter reduction
(See Table 1-13.)
(See Table 1-14.)
(See Table 1-15.)
(See Table 1-16.)
Random jitter on clock pattern 0.25 ps rms
Using 0101.. c lock pattern, amplitude = 0.5 V
p-p
Total jitter on random pattern 10 ps
p-p
Using PRBS pattern, amplitude = 0 .5 V
p-p
, measured at Bit Error Rate of 1e
-12
Interleave adjustment
(AWG70001A only)
Phase adjustment range
-180° to +180°
Phase adjustment resolution
1°
Amplitude matching range
±10% of amplitude setting
Inter-channel skew control
(AWG70002A only)
Range –100 ps to +100 ps
Resolution 1 ps
Accuracy
±5 ps
Table 1-5: SFDR, AWG70001A & AWG70002A operating at 25 GS/s
1
Analog channel
out
put frequency
In band performance
mea
sured across
Spe
cification
Adjacent band
performance
mea
sured across
Spe
cification
100 MHz
DC
–1GHz
–80 dBc
DC
–10GHz
–72 dBc
DC
– 500 MHz
DC
– 500 MHz
–70 dBc
DC
–1.5GHz
–66 dBc
D
C–1GHz
D
C–1GHz
–63 dBc
D
C–3GHz
–63 dBc
D
C–2GHz
D
C–2GHz
–62 dBc
D
C–6GHz
–60 dBc
DC–3GHz DC–3GHz
–60 dBc
DC – 6 GHz
–52 dBc
DC–5GHz DC–5GHz
–52 dBc
DC – 6 GHz
–52 dBc
5–6GHz 5–6GHz
–52 dBc
3–9GHz
–40 dBc
6–7GHz 6–7GHz
–42 dBc
4–10GHz
–42 dBc
1–6 AWG70000A Series and AWGSYNC01 Technical Reference