Tektronix AWG70002A User Manual

Specifications
Table 1-21: Trigger input (cont.)
Characteristics Description
Minimum pulse width
1kΩ selec ted
20 ns
50 Ω selected
20 ns
Trigger delay to analog output
Asynchronous trigger mode: 32,480 / (2 * fclk) ±20 ns
Synchronous trigger mode: 30,880 / (2 * fclk) ±20 ns
fclk is the frequency of the DAC sampling clock
The DAC sampling clock frequency is displayed on the clock settings tab when the external
clock output is enabled.
Trigger hold off 8320/fclk ±20 ns
fclk is the frequency of the DAC sampling clock
Trigger hold off is the amount of delay required at the end of a waveform before another trigger
pulse c an be processed.
Trigger asynchronous jitter
The asynchronous jitter performance is directly proportional the frequency o f the DA C sampling
clock. The DAC sampling clock frequency is displayed on the clock settings tab when the
external clock output is enabled.
1kΩ selected 130 ps
p-p
,26ps
rms
for 6.25 GHz DAC sampling clock
90 ps
p-p
,17ps
rms
for 12.5 GHz DAC sampling clock
50 Ω selected 105 ps
p-p
,24ps
rms
s for 6.25 GHz DAC sampling clock
70 ps
p-p
,14ps
rms
for 12.5 GHz DAC sampling clock
Trigger synchronous jitter
Clock In = 12.5 GHz: 300 fs
rms
,4.2psRJ
p-p
BER@10-12
Variable Reference In = 156.25 MHz: 400 fs
rms
s, 5.6 ps RJ
p-p
BER@10-12
Fixed Reference In = 10 MHz: 1.7 ps rms, 23.8 ps RJ
p-p
BER@10-12
Sample rate = 25 GS/s Trigger input impedance = 50 Ω
Table 1-22: Reference clock input
C
haracteristics
D
escription
C
onnector type
S
MA on rear panel
Input impedance
50 Ω (AC coupled)
Input amplitude –5 dBm to +5 dBm
Frequency range 10 MHz ±100 ppm
Variable frequency range
35 MHz to 240 MHz.
Acceptable frequency drift while the instrument is operating is ± 0.1%.
Table 1-23: Sync clock output
Characteristics Description
Connector type SMA on rear panel
Output impedance 50 Ω (AC coupled)
AWG70000A Series and AWGSYNC01 Technical Reference 1–15

Tektronix AWG70002A Specifications

General

Brand	Tektronix
Model	AWG70002A
Category	Inverter
Language	English