Xilinx Virtex-5 RocketIO GTP User Manual

Virtex-5 RocketIO GTP Transceiver User Guide www.xilinx.com 105
UG196 (v1.3) May 25, 2007
TX Buffering, Phase Alignment, and Buffer Bypass
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Table 6-8 defines the TX buffering and phase-alignment attributes.
Table 6-8: TX Buffering and Phase-Alignment Attributes
Attribute Description
OVERSAMPLE_MODE
This shared attribute activates the built-in 5x digital oversampling circuits in both
GTP_DUAL transceivers. Oversampling must be enabled when running the GTP
transceivers at line rates between 100 Mb/s and 500 Mb/s.
TRUE: Built-in 5x digital oversampling enabled for both GTP transceivers on the tile
FALSE: Digital oversampling disabled
See “Oversampling,” page 143 for more details about 5x digital oversampling.
PLL_TXDIVSEL_COMM_OUT
Divides the PLL clock to produce a high-speed TX clock. Because both edges of the
clock are used, the divided clock must run at 1/2 the desired TX line rate. Available
divider settings are 1, 2, and 4. Use this divider when the same divider value is needed
for both GTP transceivers and to provide a clock to both GTP transceivers. When
PLL_TXDIVSEL_COMM_OUT is used, both PLL_TXDIVSEL_OUT attributes must be
set to 1. See “Parallel In to Serial Out (PISO),” page 110.
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
Divides the PLL clock to produce a high-speed TX clock. Because both edges of the
clock are used, the divided clock must run at 1/2 the desired TX line rate. Available
divider settings are 1, 2, and 4. Each GTP transceiver has a separate
PLL_TXDIVSEL_OUT. When transceivers require different dividers, these attributes
must be used instead of PLL_TXDIVSEL_COMM_OUT, and
PLL_TXDIVSEL_COMM_OUT must be set to 1. See “Parallel In to Serial Out (PISO),”
page 110.
PMA_COM_CFG
Common PMA configuration attribute. Leave at the default value. Value is
automatically set by the RocketIO GTP Transceiver Wizard.
TX_BUFFER_USE_0
TX_BUFFER_USE_1
TRUE: Use the TX buffer.
FALSE: Bypass the TX buffer. The phase-alignment circuit must be used when
TX_BUFFER_USE is FALSE.
TX_XCLK_SEL0
TX_XCLK_SEL1
Selects the clock used to drive the clock domain in the PCS following the TX buffer. The
attribute must be set as follows:
TXOUT: Use when TX_BUFFER_USE = TRUE
TXUSR: Use when TX_BUFFER_USE = FALSE
TXRX_INVERT0
TXRX_INVERT1
Controls inverters that optimize the clock paths within the GTP transceiver for
different modes of operation. The attribute must be set as follows:
00000: Use when TX_BUFFER_USE = TRUE
00100: Use when TX_BUFFER_USE = FALSE

Xilinx Virtex-5 RocketIO GTP Specifications

General

Brand	Xilinx
Model	Virtex-5 RocketIO GTP
Category	Transceiver
Language	English