Xilinx Virtex UltraScale+ FPGAs User Manual

Figure 25: TX Data Transmitted
TXUSRCLK and TXUSRCLK2 Generation
The TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2. TXUSRCLK is the
internal clock for the PCS logic in the GTM transmier. The required rate for TXUSRCLK
depends on the internal datapath width of the GTM_DUAL primive and the TX line rate of the
GTM transmier. The following equaon shows how to calculate the required rate for
TXUSRCLK for all cases.
TXUSRCLK Rate =
Line Rate
Internal Datapath Width
Chapter 3: Transmitter
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Xilinx Virtex UltraScale+ FPGAs Specifications

General

Brand	Xilinx
Model	Virtex UltraScale+ FPGAs
Category	Transceiver
Language	English

Summary

Chapter 1: Transceiver and Tool Overview

Features

Key features of the GTM transceiver, including supported line rates and modulation.

UltraScale+ FPGAs GTM Transceivers Wizard

Description of the wizard tool for configuring GTM transceivers.

Chapter 2: Shared Features

Reference Clock Input/Output Structure

Reference Clock Selection and Distribution

Explanation of reference clock input options and selection architecture.

LCPLL

Reset and Initialization

Steps for initializing the GTM transceiver TX and RX datapaths.

Dynamic Reconfiguration Port

Chapter 3: Transmitter

TX Interface

Gateway to the TX datapath, including data width and clocking.

TX FEC

Details on the Integrated KP4 Reed-Solomon Forward Error Correction.

TX Pattern Generator

Generates industry-standard PRBS patterns for signal integrity testing.

TX Configurable Driver

Controls output buffer characteristics like voltage and pre-emphasis.

Chapter 4: Receiver

RX Equalizer

Compensates for channel attenuation and distortion using CTLE, FFE, and DFE.

RX CDR

Clock Data Recovery circuit for extracting clock and data from incoming streams.

RX Margin Analysis

RX Pattern Checker

RX FEC

Details on the Integrated KP4 Reed-Solomon Forward Error Correction.

RX Interface

Gateway to the RX datapath, including data width and clocking.

Chapter 5: Board Design Guidelines

Pin Description and Design Guidelines

Reference Clock