Xilinx ZCU111 User Manual

ZCU111 Board User Guide 45
UG1271 (v1.1) August 6, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
FMC Connector JTAG Bypass
When an FPGA mezzanine card (FMC) is attached to J26, it is automatically added to the
JTAG chain through electronically controlled single-pole single-throw (SPST) switch U45.
The SPST switch is normally closed and transitions to an open state when an FMC is
attached. Switch U45 adds an attached FMC to the JTAG chain as determined by the
FMCP_HSPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO
connection using a device or bypass jumper to ensure that the JTAG chain connects to the
U1 XCZU28DR RFSoC.
Clock Generation
The ZCU111 board provides fixed and variable clock sources for the XCZU28DR RFSoC.
Tab l e 3- 1 6 lists the source devices for each clock.
Table 3-16: Clock Sources
Clock (Net) Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz
U46 SI5341B clock generator
CLK_100 100 MHz
CLK_125 125 MHz
GTR_REF_CLK_SATA 125 MHz
GTR_REF_CLK_USB3 26 MHz
GTR_REF_CLK_DP 27 MHz
Programmable Frequency Clocks
USER_SI570 300 MHz (default) U47 SI570 I2C PROG. OSC.
USER_MGT_SI570 156.25 MHz (default) U49 SI570 I2C PROG. OSC.
USER_SMA_MGT_CLOCK User-provided source J14 (P)/J15 (N) SMA CONN.
SFP_SI5382_CLOCKS Variable U48 SI5382A clock recovery
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Xilinx ZCU111 Specifications

General

Brand	Xilinx
Model	ZCU111
Category	Motherboard
Language	English