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Renesas TPS-1 User Manual
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TPS
-
1 Us
er
’
s Manual: Hardware
Appendix. B Board Design Information
R19UH0081ED
0107
Rev. 1.07
page
79
of
86
Jul
30, 2018
Fig
ur
e B
-5
illus
trate
s
the power sup
ply pins and
their rec
ommended conn
ection.
Digita
l supply and di
gital grou
nd is not shown.
PHY Supply Voltages
3
.
3V
filter circuit
1.5V
PLL Voltages
(main clock generation)
PLL_AVDD - L10
PLL_
AGND
- L
9
Switching Regulartor (1.5V)
BVDD - J1
AVDD_REG - F2
BGND - G1
AGND_REG
- G
2
VDD33ESD – E12
VDDACB – H14
VDDQ
_
PECL_
B
1 –
C
8
VDDQ
_PECL
_B2 – M8
P1VDDARXTX – D14
P2VDDARXTX – L14
VDDAPLL – G14
VSSAPLLCB -
G
13
AGND – D12
AGND
–
D
13
AGND – L12
AGND
–
L12
1.0V
filter circuit
0
V
filter circuit
filter circuit
F
igure B
-5
: Voltage
Supply
Concept
78
80
Table of Contents
Default Chapter
6
Table of Contents
6
1 Overview
8
Features
8
Abstract
9
Block Diagram
10
2 Pin Function
11
Signal Overview and Description
11
Gpio Multiplexing
14
Supply Voltage Circuitry
15
Signals for Irt Communication
16
3 Host Interface
17
Testing Dpram Interface
17
Parallel Interface
17
Operating Modes of the Parallel Interface
17
Signal Description of the Parallel Interface
18
Memory Segmentation at 4 Kbyte and 16 Kbyte
20
Connection Example for a 8Bit Data Bus
22
Connection Example for a 16-Bit Data Bus
23
Spi Slave Interface
24
Serial Access to the Shared Memory
25
SPI Slave Interface Timing
28
SPI Slave Interface Reset Timing
33
4 Shared Memory Structure
34
Event Communication with the Tps-1 Firmware
36
Events from the Tps-1 Firmware to the Host
37
Events from the Host to the Tps-1 Firmware
38
Nterrupt Ommunication with the Tps-1
39
How to Generate an Interrupt by an Event
39
5 Tps-1 Boot Subsystem
43
Hardware Structure for the Boot Operation
43
Loading and Update of the Firmware During the Manufacturing Process
44
UART Interface (UART Boot)
44
SPI Master Interface (Boot Flash)
45
6 Io Local Gpio Interface
47
GPIO (Digital Input and Output)
47
Status Leds of Thetps-1
48
I2C-Bus - Lwl Diagnostic
48
7 Tps-1 Watchdog
49
Signal WD_OUT (Pin B12)
49
Signal WD_IN (Pin A11)
50
8 Profinet Io Switch
51
100Base-TX Interface
52
100Base-TX Interface (Port 1)
52
100Base-TX Interface (Port 2)
52
100Base-FX Interface (Fiber Optic)
52
100Base-FX Interface (Port 1)
53
100Base-FX Interface (Port 2)
53
I2C-Bus - Lwc Diagnostic
53
Additional Tps-1 Pins
54
Integrated Voltage Regulator 1.5 V
54
9 Clock Circuit
56
Using the Internal Clock Oscillator
56
External Clock Source
57
10 Reset of the Tps-1
58
11 Boundary Scan Interface (Jtag)
59
Circuit Recommendation of the Jtag Interface
60
Setting of Operating Modes
61
Host Interface
62
Host Parallel Interface
62
Host Serial Interface
63
IO Parallel
64
Local I/O-Configuration
64
IO Serial Interface
67
Configuration of the IO Local Parallel Interface
69
IO Local Interface
69
IO Local Parallel Interface
69
Configuration of the IO Local Serial Interface (SPI Master)
70
I&M0 Configuration (I&M0 Data) "Deleted" OK
71
Ethernet Interface Configuration
72
Copying the Configuration Data into the Boot Flash
73
Generating a Complete Serial Boot Flash Image
74
Board Design Information
75
Switching Regulator
75
Voltage Supply
75
Wiring for the Switching Regulator
76
Layout Example for Switching Regulator
77
Board Design Recommendations for Ethernet Phy
78
Supply Voltage Circuitry
78
100BASE-TX Mode Circuitry
80
Unused 100Base-TX Interface
81
100BASE-FX Mode Circuitry
82
Unused 100Base-FX Interface
85
Fast Start up Requirements
86
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Renesas TPS-1 Specifications
General
Brand
Renesas
Model
TPS-1
Category
Controller
Language
English
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