CPU 31x-2 as DP Master/DP Slave and Direct Communication
2-15
PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP
A5E00111190-01
Address areas of the transfer memory
Configure the I/O address areas in STEP 7:
you can configure up to 32 I/O address areas
the maximum length of each one of these address areas is 32 bytes
You can configure a maximum of 244 bytes for inputs and 244 bytes for
outputs.
The table below shows the principle of address areas. You can also find this figure
in the STEP 7 configuration.
Table 2-5 Example of an address area configuration for transfer memory
Typ
e
Master
Address
Typ
e
Slave
Address
Lengt
h
Unit Consistenc
y
1 E 222 A 310 2 Byte Unit
2A 0 E 13 10 Word Total length
:
32
Address areas in the
DP Master CPU
Address areas in the
DP Slave CPU
These address area parameters
must be the same for both the DP
Master and DP Slave
Rules
The following rules must be followed when using the intermediate memory:
Address area assignment:
– Input data of the DP slave are always output data of the DP master
– Output data of the DP slave are always input data of the DP master
The addresses can be freely allocated. In the user program, access the data
with Load/Transfer statements or with SFCs 14 and 15. You can also specify
addresses from the I/O process images.
Note
Transfer memory addresses are assigned from the DP address area of the CPU
31x-2.
Do not assign transfer memory addresses to the I/O modules in the CPU 31x-2!
The lowest address represents the start address of the respective address
area.
Length, unit and consistency of DP Master/Slave address areas related to each
other must be identical.
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