Cycle and Reaction times
3-16
PLC S7-300, CPU Specifications CPU 312 IFM to CPU 318-2 DP
A5E00111190-01
3.5 Calculation Example for the Interrupt Response Time
Parts of the Interrupt Response Time
As a reminder: The process interrupt response time is formed by:
Response time of the CPU to process interrupt and
the response time of the signal module to process interrupt.
Example: Your S7-300 assembly consists of a CPU 314 and four digital modules.
One digital input module is the SM 321; DI 16DC 24V; with hardware/diagnostic
interrupt configuration. In your CPU and SM configuration you have enabled only
process interrupt. You decided not to use time-controlled processing, diagnostics
or error handling. You configured an input delay of 0.5 ms for the digital input
module. No activities are necessary at the scan cycle checkpoint. There is no
communication via the MPI.
Calculation
In this example, the response time to process interrupt is calculated from following
times:
Response time of CPU 314 to process interrupt: approx. 1.1 ms
Process interrupt response time of SM 321; DI 16DC 24V:
– Internal interrupt preparation time:
0.25 ms
– Input delay 0.5 ms
The process interrupt response time is formed by the sum of all specified times:
Process interrupt response time = 1.1 ms + 0.25 ms + 0.5 ms = approx. 1.85 ms.
This calculated process interrupt response time represents the time expiring
between an incoming signal at the digital input and the first instruction in OB40.
3.6 Reproducibility of Delay and Watchdog Interrupts
Definition of Reproducibility
Delay Interrupt:
The interval between the call-up of the first instruction in the OB and the
programmed time of the interrupt.
Watchdog Interrupt:
The fluctuation of the time interval between two successive call-ups, measured in
each case between the first instruction in the OB.
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