22 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 1: Introduction
Table 1-6: IBERT v2.0 Core for the Virtex-6 FPGA GTH Transceivers
Feature Description
Multiple GTH Transceivers Up to sixteen transceivers can be selected per design
Pattern Generator One pattern generator per selected GTH transceiver (four
per QUAD) is used. PRBS 7-bit, PRBS 15-bit PRBS 23-bit,
PRBS 31-bit, Clk 2x, and Clk 10x patterns are available. The
desired pattern from that set can be selected individually
for each GTH transceiver at runtime.
Pattern Checker One pattern checker per selected GTH transceiver is used
(four per QUAD). The same pattern set is available as the
pattern generator. The pattern can be chosen for each GTH
transceiver at runtime.
Fabric Width The FPGA fabric interface to the GTH QUAD can be either
16- or 20-bits wide and selectable at generate time.
BERT Parameters Number of bits received in error and total number of words
received are gathered dynamically and read out by the
ChipScope Pro Analyzer tool.
Polarity The polarity of the TX or RX side of each GTH transceiver
can be changed at runtime.
Reset The BER counters for each GTH transceiver can be reset
independently. A reset is also available for the entire GTH
QUAD, including PLLs.
Link and Lock Status Link, DCM, and PLL lock status are gathered for each GTH
transceiver in the core.
DRP Read The DRP space for each GTH transceiver can be read
independently of all others.
DRP Write The contents of the DRP for each GTH transceiver can be
changed at runtime, with single-bit granularity.
Ports Read The contents of the registers that monitor the GTH
transceiver ports can be read independently of others.
Ports Write The contents of the registers that control the GTH
transceiver ports can be changed at runtime.
Status The dynamic status information for the entire core can be
read out of the core at runtime.
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