Xilinx ChipScope Pro User Manual

ChipScope Pro Software and Cores User Guide www.xilinx.com 47
UG029 (v14.3) October 16, 2012
ChipScope Pro Core Inserter Features
Core Utilization
The ATC2 Core Generator has a core resource utilization monitor that estimates the
number of look-up tables (LUTs) and flip-flops (FF) used by the ATC2 core, depending on
the parameters used. The ATC2 core never uses block RAM or additional clock resources
(for example, BUFG or DCM components).
Choosing Net Connections for ILA Signals
The Net Connections tab allows you to choose the signals to connect to the ILA core. If
trigger is separate from data, then the clock, trigger, and data ports must be specified. When
trigger equals data, only the clock and trigger/data ports must be specified. Double-click
the CLOCK PORT label or click the plus sign (+) next to it to expand. No connection has
been made, so the connection appears in red.
The ATC2 Net Connections tab allows you to choose the signals to connect to the ATC2
core. The clock and data ports must be specified. Expand the Clock Net label. No
connection has been made, so the connection appears in red.
To change any core connection, select Modify Connections. The Select Net dialog box now
appears. This dialog box provides an easy interface to choose nets to connect to the ILA or
ATC2 cores. The hierarchical structure of the design can be traversed using the
Structure/Nets pane on the upper left of the Select Net dialog box. All the nets for the
selected structure hierarchy level of the design appear in the table on the lower left pane of
the Select Net dialog box. The following net information is displayed in this table:
• Net Name: The name of the net as it appears in the EDIF netlist. The net name might
be different than the corresponding signal name in the HDL source due to renaming
and other optimizations during synthesis.
• Source Instance: The instance name of the lower-level hierarchical component from
which the net at the current level of hierarchy is driven. The source instance does not
necessarily describe the originating driver of the net.
• Source Component: The type of component described by the Source Instance.
• Base Type: The type of the lowest level driving component of the net. The base type is
either a primitive or black box component.
All the net identifiers described above can be filtered for key phrases using the Pattern text
box and Filter button. Also, nets can be sorted in ascending and descending order based on
the various net identifiers by selecting the appropriate net identifier button in the column
headers of the net selection table.
Note: The net names are sorted in alpha-numeric or “bus element” order whenever possible.
Common delimiters such as “[“, “(“, etc., are used to identify possible bus element nets.
The tabs for clock, data, and trigger inputs of the ILA core appear in the pane at the upper
right of the Select Net dialog box. If you are selecting nets for an ATC2 core, only the Clock
and Data input port categories appear at the upper right of the Select Net dialog box. If
multiple trigger or data ports exist, there are multiple sub-tabs on the bottom of the Net
Selections pane, respectively. Nets that are selected at a given level of hierarchy can be
connected to inputs of the ILA or ATC2 capture cores by following these steps:
1. In the lower-left table of the Select Net dialog box, select the net(s) that you want to
connect to the capture core.
Note: You can select multiple nets to connect to an equivalent number of capture core input
connections. Hold down the Shift key and use the left mouse button to select contiguous nets.
Use a combination of the Ctrl key and left mouse button to select non-contiguous nets. You can

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English