Xilinx ChipScope Pro User Manual

34 www.xilinx.com ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Chapter 3: Using the ChipScope Pro Core Inserter
ChipScope Definition and Connection Source File
To use the ChipScope Pro Core Inserter tool to insert cores into a design processed by
Project Navigator:
1. Add the definition and connection file (.cdc) to the project and associate it with the
appropriate design module.
a. To create a new .cdc file, select Project > New Source, then select ChipScope
Definition and Connection File and give the file a name. Click Next to advance to
the Summary panel, then click Finish to create the file.
Note: The ChipScope Definition and Connection File source type is only listed if Project
Navigator detects a ChipScope Pro installation (software versions must match).
b. To add an existing .cdc file, select Project > Add Source or Project > Add Copy of
Source, then browse for the existing .cdc file.
After selecting the .cdc file in the file browser, click Open and then click OK on the
Adding Source Files dialog box. The .cdc file now displays in the Sources in Project
window underneath the associated design module.
2. To create the cores and complete the signal connections, double-click the .cdc file in the
Design panel. This runs the Synthesis (if applicable) and Translate processes, as
necessary, and then opens the .cdc file in the ChipScope Pro Core Inserter tool.
3. Modify the cores and connections in the ChipScope Pro Core Inserter tool as necessary
(as shown in
“ChipScope Pro Core Inserter Features,” page 38), then close the
ChipScope Pro Core Inserter tool.
4. When the associated top-level design is implemented in Project Navigator, the cores
are automatically inserted into the design netlist as part of the Translate phase of the
flow. There is no need to set any properties to enable this to happen. The .cdc is in the
project and associated with the design module being implemented and causes the
cores to be inserted automatically.
Useful Project Navigator Settings
The following Project Navigator settings help you implement a design with cores.
If you use the XST synthesis tool, set the Keep Hierarchy option to Yes or Soft to preserve
the design hierarchy and prevent the XST tool from optimizing across all levels of
hierarchy in your design. Using the Keep Hierarchy option preserves the names of nets
and other recognizable components during the core insertion stage of the flow. If you do
not use the Keep Hierarchy option, some of your nets and/or components can be
combined with other logic into new components or otherwise optimized away. To keep the
design hierarchy:
″ Right-click the Synthesize - XST process and select Process Properties.
″ In the Synthesis Options category, make sure the Keep Hierarchy property is set to
Soft or Yes and click OK.

Xilinx ChipScope Pro Specifications

General

Brand	Xilinx
Model	ChipScope Pro
Category	Computer Hardware
Language	English