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ChipScope Pro Software and Cores User Guide
UG029 (v14.3) October 16, 2012
Appendix B:
References
Ot
he
r
ref
e
ren
ce
s
:
24.
ActiveState
25.
Agilent T
echnologies
26.
T
cl Developer Xchange
27.
Byte T
ools
28.
UG480,
7 Series FPGAs XADC Dual 12-Bit MSPS An
alog-to-Digital Converter User Guide
225
Table of Contents
ChipScope Pro Software and Cores User Guide
1
Revision History
2
Introduction
5
ChipScope Pro Tools Overview
5
ChipScope Pro Tools Description
5
Design Flow
8
Using ChipScope Pro Cores in the PlanAhead Tool
8
Using ChipScope Pro Cores in Embedded Processor and DSP Tool Flows
9
ChipScope Pro Cores Description
10
ICON Core
10
ILA Core
10
ILA Trigger Input Logic
10
ILA Trigger Output Logic
14
ILA Data Capture Logic
15
ILA Control and Status Logic
16
VIO Core
16
Activity Detectors
16
Pulse Trains
16
ATC2 Core
17
ATC2 Core Data Path Description
17
ATC2 Core Data Capture and Run-Time Control
17
IBERT Core
18
IBERT Design Flow
18
IBERT Feature Descriptions
18
System Requirements
28
Operating System Requirements
28
Software Tools Requirements
28
Communications Requirements
29
Board Requirements
30
Software Installation and Licensing
30
Using the Core Generator Tools
31
Overview
31
Using the Xilinx CORE Generator Tool with ChipScope Pro Cores
31
Core Generation
31
Generating Cores for ICON, ILA, VIO and ATC2 Cores
31
Generating IBERT v2.0 Cores
32
Using the ChipScope Pro Core Inserter
33
ChipScope Pro Core Inserter Overview
33
Using the ChipScope Pro Core Inserter with the PlanAhead Tool
33
Using the ChipScope Pro Core Inserter with ISE Project Navigator
33
ChipScope Definition and Connection Source File
34
Useful Project Navigator Settings
34
Using the ChipScope Pro Core Inserter with Command Line Implementation
35
Command Line Flow Overview
35
Create CDC Project Step
36
Edit CDC Project Step
37
Insert Cores Step
37
ChipScope Pro Core Inserter Features
38
Working with Projects
38
Opening an Existing Project
38
Saving Projects
38
Refreshing the Netlist
38
Inserting and Removing Units
39
Setting Preferences
39
Inserting the Cores
39
Exiting the ChipScope Pro Core Inserter
39
Specifying Input and Output Files
39
Project Level Parameters
39
Selecting the Target Device Family
39
Using SRLs
39
Using RPMs
40
Core Utilization
40
Choosing ICON Options
40
Selecting the Boundary Scan Chain
40
Choosing ILA Trigger Options and Parameters
40
Selecting the Number of Trigger Ports
40
Entering the Width of the Trigger Ports
41
Selecting the Number of Trigger Match Units
41
Selecting the Match Unit Type
41
Selecting Match Unit Counter Width
42
Enabling the Trigger Condition Sequencer
42
Enabling the Storage Qualification Condition
43
Enabling the Trigger Output Port
43
Choosing ILA Core Capture Parameters
43
Selecting the Data Depth
43
Entering the Data Width
44
Selecting the Data Type
44
Selecting the Data-Same-As-Trigger Ports
44
Choosing ATC2 Data Capture Settings
44
Capture Mode
44
Max Frequency Range
45
Enable Auto Setup
45
Enable "Always On" Mode
45
Pin Edit Mode
45
ATD Pin Count
45
Endpoint Type
45
Signal Bank Count
45
TDM Rate
46
Data Width
46
Pin Parameters
46
Core Utilization
47
Choosing Net Connections for ILA Signals
47
Adding Units
48
Inserting Cores into Netlist
48
Managing Project Preferences
49
Using the ChipScope Pro Analyzer
51
ChipScope Pro Analyzer Overview
51
ChipScope Pro Analyzer Server Interface
51
ChipScope Pro Analyzer Client Interface
52
Project Tree
52
Signal Browser
53
Renaming Signals, Buses, and Triggers Ports
53
Adding/Removing Signals from Views
53
Combining and Adding Signals Into Buses
53
Reverse Bus Ordering
54
Bus Radices
54
Deleting Buses
55
Type and Activity Persistence (VIO only)
55
Message Pane
56
Main Window Area
56
ChipScope Pro Analyzer Features
56
Working with Projects
56
Creating and Saving A New Project
56
Saving Projects
56
Printing Waveforms
56
Print Wizard (1 of 3) Window
57
Print Wizard (2 of 3) Window
58
Print Wizard (3 of 3) Window
58
Page Setup
59
Importing Signal Names
59
Exporting Data
59
Closing and Exiting the ChipScope Pro Analyzer
60
Viewing Options
60
Setting up a Server Host Connection
60
Opening a Parallel Cable Connection
60
Opening a Platform Cable USB Connection
61
Selecting the USB Port
61
Blinking the LED on the Cable
61
Selecting the Cable Speed
61
Opening a Digilent USB JTAG Cable
61
Selecting the Cable Device
61
Selecting the Cable Speed
61
Using Multiple Platform Cable USB Connections
62
Connecting Multiple Xilinx JTAG Cables to One Machine
62
Setting Up ChipScope Pro Analyzer tool to Use Multiple Instances of cs_server
62
Starting and Configuring Multiple Instances of ChipScope Pro Analyzer
62
Opening a JTAG Chain Plug-in Connection
62
Polling the Auto Core Status
63
Configuring the Target Device(s)
63
Setting Up the Boundary Scan (JTAG) Chain
63
Device Configuration
63
Observing the Configuration Progress
64
Displaying JTAG User and ID Codes
64
Displaying Configuration Status Information
65
Trigger Setup Window
65
Capture Settings
65
Match Functions
67
Trigger Conditions
68
Saving and Recalling Trigger Setups
69
Running/Arming the Trigger
69
Stopping/Disarming the Trigger
70
Trigger Run Modes
70
Trigger and Capture Status
72
Waveform Window
73
Bus and Signal Reordering
73
Cut/Copy/Paste/Delete Signals and Buses
73
Zooming In and Out
73
Centering the Waveform
74
Cursors
74
Sample Display Numbering
74
Displaying Markers
74
Data Capture Time Stamp
74
Listing Window
74
Bus and Signal Reordering
75
Removing Signals/Buses
75
Cursors
75
Go to Cursors
75
Bus Plot Window
75
Plot Type
75
Display Type
76
Bus Selection
76
Min/Max
76
Cursor Tracking
76
VIO Console Window
76
Bus/Signal Column
76
Value Column
77
VIO Core Menu and Toolbar Controls
78
System Monitor
79
System Monitor Console
79
System Monitor Console Toolbar
80
System Monitor Data Logging
81
IBERT v2.0 Console Window for Virtex-5 FPGA GTX Transceivers
81
MGT/BERT Settings Panel
81
DRP Settings Panel
83
Port Settings Panel
84
Sweep Test Settings Panel
84
IBERT v2.0 Virtex-5 FPGA GTX Transceiver Toolbar and Menu Options
86
IBERT Console Window for Virtex-6 FPGA GTX Transceivers
86
MGT/BERT Settings Panel
87
DRP Settings Panel
89
Port Settings Panel
89
Sweep Test Settings Panel
89
Sweep Test Log
91
IBERT Virtex-6 FPGA GTX Transceiver Toolbar and Menu Options
92
IBERT Console Window for Virtex-6 FPGA GTH Transceivers
92
MGT/BERT Settings Panel
93
DRP Settings Panel
94
Port Settings Panel
94
IBERT Virtex-6 FPGA GTH Transceiver Sweep Test Panel
95
IBERT Virtex-6 FPGA GTH Transceiver Toolbar and Menu Options
97
IBERT Console Window for Spartan-6 FPGA GTP Transceivers
98
MGT/BERT Settings Panel
98
DRP Settings Panel
100
Port Settings Panel
100
IBERT Spartan-6 FPGA GTP Sweep Test Panel
101
IBERT Spartan-6 FPGA GTP Toolbar and Menu Options
102
IBERT Console Window for 7 Series FPGA GTX Transceivers
103
MGT/BERT Settings Panel
103
DRP Settings Panel
105
Port Settings Panel
105
RX Margin Analysis Panel
106
IBERT 7 Series FPGA GTX Transceiver Toolbar and Menu Options
109
IBERT Console Window for 7 Series FPGA GTH Transceivers
109
MGT/BERT Settings Panel
110
DRP Settings Panel
111
Port Settings Panel
112
RX Margin Analysis Panel
112
IBERT 7 Series FPGA GTH Transceiver Toolbar and Menu Options
115
IBERT Console Window for 7 Series FPGA GTP Transceivers
116
MGT/BERT Settings Panel
116
DRP Settings Panel
118
Port Settings Panel
118
RX Margin Analysis Panel
118
IBERT 7 Series FPGA GTP Transceiver Toolbar and Menu Options
121
IBERT Console Window for 7 Series FPGA GTZ Transceivers
122
MGT/BERT Settings Panel
122
DRP Settings Panel
123
Port Settings Panel
124
RX Margin Analysis Panel
124
IBERT 7 Series FPGA GTZ Transceiver Toolbar and Menu Options
127
Standalone IBERT Sweep Test Plot Viewer
128
Help Pages
128
ChipScope Pro ILA Waveform Toolbar Features
128
ChipScope Pro Analyzer Command Line Options
129
Optional Arguments
129
Windows Command Line Example
130
ChipScope Engine Tcl Interface
131
Overview
131
Requirements
131
Limitations
131
CSE/Tcl Command Summary
132
CseJtag Tcl Commands
132
CseFpga Tcl Commands
134
CseCore Tcl Commands
136
CseVIO Tcl Commands
136
CseJtag Tcl Commands
137
::chipscope::csejtag_session create
138
Syntax
138
Arguments
138
Returns
138
Example
138
::chipscope::csejtag_session destroy
139
Syntax
139
Arguments
139
Returns
139
Example
139
::chipscope::csejtag_session get_api_version
139
Syntax
139
Arguments
139
Returns
139
Example
139
::chipscope::csejtag_session send_message
140
Syntax
140
Arguments
140
Returns
140
Example
140
::chipscope::csejtag_target open
141
Syntax
141
Arguments
141
Returns
142
Example
142
::chipscope::csejtag_target close
143
Syntax
143
Arguments
143
Returns
143
Example
143
::chipscope::csejtag_target is_connected
144
Syntax
144
Arguments
144
Returns
144
Example
144
::chipscope::csejtag_target lock
145
Syntax
145
Arguments
145
Returns
145
Example
145
::chipscope::csejtag_target unlock
146
Syntax
146
Arguments
146
Returns
146
Example
146
::chipscope::csejtag_target get_lock_status
147
Syntax
147
Arguments
147
Returns
147
Example
147
::chipscope::csejtag_target clean_locks
148
Syntax
148
Arguments
148
Returns
148
Example
148
::chipscope::csejtag_target flush
149
Syntax
149
Arguments
149
Returns
149
Example
149
::chipscope::csejtag_target set_pin
150
Syntax
150
Arguments
150
Returns
150
Example
150
::chipscope::csejtag_target get_pin
151
Syntax
151
Arguments
151
Returns
151
Example
151
::chipscope::csejtag_target pulse_pin
152
Syntax
152
Arguments
152
Returns
152
Example
152
::chipscope::csejtag_target wait_time
153
Syntax
153
Arguments
153
Returns
153
Example
153
::chipscope::csejtag_target get_info
154
Syntax
154
Arguments
154
Returns
154
Example
154
::chipscope::csejtag_tap autodetect_chain
155
Syntax
155
Arguments
155
Returns
155
Example
155
::chipscope::csejtag_tap interrogate_chain
156
Syntax
156
Arguments
156
Returns
156
Example
156
::chipscope::csejtag_tap get_device_count
157
Syntax
157
Arguments
157
Returns
157
Example
157
::chipscope::csejtag_tap set_device_count
158
Syntax
158
Arguments
158
Returns
158
Example
158
::chipscope::csejtag_tap get_irlength
159
Syntax
159
Arguments
159
Returns
159
Example
159
::chipscope::csejtag_tap set_irlength
160
Syntax
160
Arguments
160
Returns
160
Example
160
::chipscope::csejtag_tap get_device_idcode
161
Syntax
161
Arguments
161
Returns
161
Example
161
::chipscope::csejtag_tap set_device_idcode
162
Syntax
162
Arguments
162
Returns
162
Example
162
::chipscope::csejtag_tap navigate
163
Syntax
163
Arguments
163
Returns
163
Example
163
::chipscope::csejtag_tap shift_chain_ir
164
Syntax
164
Arguments
164
Returns
164
Example
165
::chipscope::csejtag_tap shift_device_ir
166
Syntax
166
Arguments
166
Returns
167
Example
167
::chipscope::csejtag_tap shift_chain_dr
168
Syntax
168
Arguments
168
Returns
168
Example
169
::chipscope::csejtag_tap shift_device_dr
170
Syntax
170
Arguments
170
Returns
171
Example
171
::chipscope::csejtag_db add_device_data
172
Syntax
172
Arguments
172
Returns
172
Example
172
::chipscope::csejtag_db lookup_device
173
Syntax
173
Arguments
173
Returns
173
Example
173
::chipscope::csejtag_db get_device_name_for_idcode
174
Syntax
174
Arguments
174
Returns
174
Example
174
::chipscope::csejtag_db get_irlength_for_idcode
175
Syntax
175
Arguments
175
Returns
175
Example
175
::chipscope::csejtag_db parse_bsdl
176
Syntax
176
Arguments
176
Returns
176
Example
176
::chipscope::csejtag_db parse_bsdl_file
177
Syntax
177
Arguments
177
Returns
177
Example
177
CseFpga Tcl Commands
178
::chipscope::csefpga_configure_device
179
Syntax
179
Arguments
179
Returns
180
Example
180
::chipscope::csefpga_configure_device_with_file
181
Syntax
181
Arguments
181
Returns
181
Example
181
::chipscope::csefpga_get_config_reg
182
Syntax
182
Arguments
182
Returns
182
Example
182
::chipscope::csefpga_get_instruction_reg
183
Syntax
183
Arguments
183
Returns
183
Example
183
::chipscope::csefpga_get_usercode
184
Syntax
184
Arguments
184
Returns
184
Example
184
::chipscope::csefpga_get_user_chain_count
185
Syntax
185
Arguments
185
Returns
185
Example
185
::chipscope::csefpga_is_config_supported
186
Syntax
186
Arguments
186
Returns
186
Example
186
::chipscope::csefpga_is_configured
187
Syntax
187
Arguments
187
Returns
187
Example
187
::chipscope::csefpga_is_sys_mon_supported
188
Syntax
188
Arguments
188
Returns
188
Example
188
::chipscope::csefpga_run_sys_mon_command_sequence
189
Syntax
189
Arguments
189
Returns
189
Example
189
::chipscope::csefpga_get_sys_mon_reg
190
Syntax
190
Arguments
190
Returns
190
Example
190
::chipscope::csefpga_set_sys_mon_reg
191
Syntax
191
Arguments
191
Returns
191
Example
191
CseCore Tcl Commands
192
::chipscope::csecore_get_core_count
192
Syntax
192
Arguments
192
Returns
192
Example
192
::chipscope::csecore_get_core_status
193
Syntax
193
Arguments
193
Returns
193
Example
193
::chipscope::csecore_is_cores_supported
194
Syntax
194
Arguments
194
Returns
194
Example
194
CseVIO Tcl Commands
195
::chipscope::csevio_get_core_info
195
Syntax
195
Arguments
195
Returns
196
Example
196
::chipscope::csevio_is_vio_core
197
Syntax
197
Arguments
197
Returns
197
Example
197
::chipscope::csevio_init_core
198
Syntax
198
Arguments
198
Returns
198
Example
198
::chipscope::csevio_terminate_core
199
Syntax
199
Arguments
199
Returns
199
Example
199
::chipscope::csevio_define_signal
200
Syntax
200
Arguments
200
Returns
200
Example
200
::chipscope::csevio_define_bus
201
Syntax
201
Arguments
201
Returns
201
Example
201
::chipscope::csevio_undefine_name
202
Syntax
202
Arguments
202
Returns
202
Example
202
::chipscope::csevio_write_values
203
Syntax
203
Arguments
203
Returns
203
Example
203
::chipscope::csevio_read_values
204
Syntax
204
Arguments
204
Returns
204
Example
204
CSE/Tcl Examples
205
ChipScope Pro Tools Troubleshooting Guide
207
Overview
207
ChipScope Pro Tools Installation Troubleshooting
208
Xilinx JTAG Programming Cable Troubleshooting
209
ChipScope Pro Analyzer Core Troubleshooting
217
Gathering Information for Xilinx Technical Support
223
Obtaining Xinfo Information
223
On Windows
223
On Linux
223
Obtaining ChipScope Pro Analyzer Log File Information
223
On Windows
223
On Linux
223
Obtaining ChipScope Pro Core Inserter Tool Log File Information
223
On Windows
223
On Linux
223
Obtaining an Archived ISE Tool Project
223
References
225
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Xilinx ChipScope Pro Specifications
General
Brand
Xilinx
Model
ChipScope Pro
Category
Computer Hardware
Language
English
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