Xilinx VC707 User Manual

VC707 Evaluation Board www.xilinx.com 25
UG885 (v1.4) May 12, 2014
Feature Descriptions
Table 1-8 lists the SD card interface connections to the FPGA.
USB JTAG
[Figure 1-2, callout 6]
JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration
logic module (U26) where a host computer accesses the VC707 board JTAG chain through
a type-A (host side) to micro-B (VC707 board side) USB cable.
X-Ref Target - Figure 1-6
Figure 1-6: SD Card Interface
UG885_c1_06_021412
TXB0108
Voltage-Level
Translator
U31
A7
A6
A5
A4
A3
A2
A1
VCCA
B7
B6
B5
B4
B3
B2
B1
VCCB
A8 B8
OE
GND
SDIO Card
Connector
U29
DETECT
DAT2
DAT1
DAT0
CLK
CMD
CD_DAT3
VDD
PROTECT
GNDTAB2VSS1
GNDTAB1
VSS2
GND
GND
SDIO_SDWP
11
SDIO_SDDET
10
SDIO_DAT2
9
SDIO_DAT1
8
SDIO_DAT0 7
SDIO_CLK
5
SDIO_CMD
1SDIO_CD_DAT3
VCC3V3
C52
0.1μF 25V
X5R
GND
4
6
3
D_P
NC 12
GNDTAB3
GNDTAB4
IOGND1
IOGND2
15
16
17
18
13
14
51.1K 1% Six Places
VCC3V3
R318
R319
R316
R317
R314
R315
2
VCC1V8
C51
0.1μF 25V
X5R
GND
GND
VCC3V3
C50
0.1μF 25V
X5R
GND
SDIO_DAT2_LS
SDIO_DAT1_LS
SDIO_DAT0_LS
SDIO_CLK_LS
SDIO_CMD_LS
SDIO_CD_DAT3_LS
51.1K 1% Six Places
R312
R313
R310
R311
R308
R309
NC
NC
VCC1V8
R35
R34
4.7K
4.7K
To
FPGA
Bank 13
(U1)
To
FPGA
Bank 12
(U1)
Table 1-8: SDIO Connections to the FPGA
FPGA (U1)
Pin
Schematic Net Name
Level Shifter (U31) SDIO Connector (U29)
Pin Number Pin Name Pin Number Pin Name
AR32 SDIO_SDWP N/A N/A 11 SDWP
AP32 SDIO_SDDET N/A N/A 10 SDDET
AP30 SDIO_CMD_LS 6 A5 2 CMD
AN30 SDIO_CLK_LS 7 A6 5 CLK
AV31 SDIO_DAT2_LS 4 A3 9 DAT2
AU31 SDIO_DAT1_LS 3 A2 8 DAT1
AR30 SDIO_DAT0_LS 1 A1 7 DAT0
AT30 SDIO_CD_DAT3_LS 5 A4 1 CD_DAT3
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Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English