VC707 Evaluation Board www.xilinx.com UG885 (v1.4) May 12, 2014
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/05/12 1.0 Initial Xilinx release.
10/08/12 1.1 Chapter 1, VC707 Evaluation Board Features: In Table 1-1, notes for J37 changed to
Samtec ASP_134486_01. The board photo in Figure 1-2 was replaced. In Table 1-3, GPGA
(U1) Bank 32 was deleted. A note was added about the user clock for Figure 1-10. In
Table 1-15, FPGA pin AN1 changed to AM4 and pin AN2 changed to AM3. In
SGMII
GTX Transceiver Clock Generation, page 42,
25 MHz LVDS clock changed to 125 MHz
LVDS clo
ck. The Figure 1-10 title also changed from 25 MHz to 125 MHz. In Table 1-23,
pin AR42 changed to AT42. In Figure 1-33, switching regulator supply voltage UG63 for
MGTVCCAUX was updated. In Table 1-29, device type PTD08D021W (V
OUT
A) power
rail voltage changed to 1.80V. In Table 1-32, values for rail number 3 changed. In
Appendix C, Master Constraints File Listing, the entire listing was replaced.
Appendix G, Regulatory and Compliance Information now includes a link to the
Declaration of Conformity and markings for waste electrical and electronic equipment
(WEEE), restriction of hazardous substances (RoHS), and CE compliance.
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