Xilinx VC707 User Manual

28 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Chapter 1: VC707 Evaluation Board Features
Clock Generation
The VC707 board provides five clock sources for the FPGA. Table 1-9 lists the source
devices for each clock.
Table 1-10 lists the pin-to-pin connections from each clock source to the FPGA.
Table 1-9: VC707 Board Clock Sources
Clock Name
Clock
Source
Description
System Clock
U51
SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (SiTime).
See System Clock (SYSCLK_P and SYSCLK_N), page 29
User Clock
U34
Si570 3.3V LVDS I
2
C Programmable Oscillator, 156.250 MHz default (Silicon Labs).
See Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N), page 29
User SMA Clock
(differential pair)
J31
USER_SMA_CLOCK_P (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N),
page 30.
J32
USER_SMA_CLOCK_N (Net name).
See User SMA Clock (USER_SMA_CLOCK_P and USER_SMA_CLOCK_N),
page 30.
GTX SMA REF Clock
(differential pair)
J25
SMA_MGT_REFCLK_C_P (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page 31
J26
SMA_MGT_REFCLK_C_N (Net name).
See GTX SMA Clock (SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N), page 31
Jitter Attenuated
Clock
U24
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs).
See Jitter Attenuated Clock, page 31
Table 1-10: Clock Connections, Source to FPGA
Clock Source Pin Net Name FPGA (U1) Pin
U51.5 SYSCLK_N E18
U51.4 SYSCLK_P E19
U34.5 USER_CLOCK_N AL34
U34.4 USER_CLOCK_P AK34
J26.1 SMA_MGT_REFCLK_N AK7
J25.1 SMA_MGT_REFCLK_P AK8
J32.1 USER_SMA_CLOCK_N AK32
J31.1 USER_SMA_CLOCK_P AJ32
U24.29 Si5324_OUT_N AD7
U24.28 Si5324_OUT_P AD8
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Xilinx VC707 Specifications

General

Form Factor	ATX
FPGA Device	XC7VX485T
FPGA Family	Virtex-7
Logic Cells	485, 760
DSP Slices	2, 800
Operating Temperature	0°C to +85°C
Flash Memory	128 Mb (for configuration)
Configuration	JTAG, SPI Flash
Connectivity	USB
Expansion Connectors	FMC
USB	USB 2.0
PCIe Gen2/Gen3 Support	Yes
Ethernet	1 Gbps
Power Supply	ATX

Summary

Chapter 1: VC707 Evaluation Board Features

Overview

General introduction to the VC707 board and its features.

Additional Information

Refers to external resources for additional information about the board.

Feature Descriptions

Detailed descriptions of the VC707 board's hardware components and interfaces.

Virtex-7 FPGA

Details about the main FPGA chip on the VC707 board.

DDR3 Memory

Information about the 1 GB DDR3 SODIMM memory module.

Linear BPI Flash Memory

Details on the 128 MB nonvolatile flash memory for configuration or storage.

USB 2.0 ULPI Transceiver

Information on the USB 2.0 PHY for host computer connectivity.

SD Card Interface

Description of the SDIO interface for user-logic access to memory cards.

USB JTAG

Details about the onboard USB-to-JTAG configuration logic module.

Clock Generation

Information on the five clock sources provided for the FPGA.

GTX Transceivers

Details on the 27 GTX transceivers and their connectivity.

PCI Express Connectivity

Information on the 8-lane PCI Express edge connector and data transfer rates.

Ethernet PHY

Information on the Marvell Alaska PHY device for Ethernet communications.

HDMI Video Output

Information on the HDMI video output using the Analog Devices ADV7511.

I2C Bus

Description of the I2C port and bus switch on the board.

Status LEDs

Definition and description of the status LEDs on the board.

User Controls

Details on user LEDs, pushbuttons, DIP switches, rotary switches, and SMA connectors.

Power On/Off Switch

Details about the power on/off slide switch.

FPGA_PROG_B Pushbutton

Information about the FPGA programming pushbutton.

Configuration Mode Switch

Details on DIP switch SW11 for configuration mode and flash address.

FMC Connectors

Details on the VITA 57.1 FMC1 and FMC2 HPC connectors.

Power Management

Overview of the board's power distribution system.

XADC Analog-to-Digital Converter

Details about the XADC block and its capabilities.

Appendix A: Default Switch and Jumper Settings

GPIO DIP Switch SW2

Default settings for the 8-position GPIO DIP switch SW2.

Configuration DIP Switch SW11

Default settings for SW11, controlling configuration mode and flash address.

Default Jumper Settings

List of default jumper positions for various board connectors.

Appendix B: VITA 57.1 FMC Connector Pinouts

FMC1 HPC Connector Pinout

Pinout diagram for the FMC1 HPC connector (J35).

FMC2 HPC Connector Pinout

Pinout diagram for the FMC2 HPC connector (J37).

Appendix C: Master Constraints File Listing

VC707 Board XDC Listing

Master Xilinx design constraints (XDC) file template for VC707 board designs.

Appendix D: Board Setup

Installing VC707 Board in a PC Chassis

Step-by-step guide for installing the board into a PC chassis.

Appendix E: Board Specifications

Dimensions

Physical dimensions of the VC707 evaluation board.

Environmental Specifications

Operating temperature, storage, and humidity specifications.

Appendix F: Additional Resources

References

List of websites and documents for up-to-date information and supplemental material.

Appendix G: Regulatory and Compliance Information

Declaration of Conformity

Details on the product's conformity to EU directives and standards.

Electromagnetic Compatibility

Information on radio disturbance and immunity characteristics.

Safety Information

Safety requirements for information technology equipment.