Xilinx VC707 User Manual

VC707 Evaluation Board www.xilinx.com 29
UG885 (v1.4) May 12, 2014
Feature Descriptions
System Clock (SYSCLK_P and SYSCLK_N)
[Figure 1-2, callout 7]
The VC707 board has a LVDS 200 MHz oscillator (U51) soldered onto the back side of the
board and wired to an FPGA MRCC clock input on bank 38. This 200 MHz signal pair is
named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins E19 and E18
respectively.
• Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
• PPM frequency jitter: 50 ppm
• Differential Output
For more details, see the SiTime SiT9102 data sheet [Ref 18]. The system clock circuit is
shown in Figure 1-9.
Programmable User Clock (USER_CLOCK_P and USER_CLOCK_N)
[Figure 1-2, callout 8]
The VC707 board has a programmable low-jitter 3.3V differential oscillator (U34)
connected to the FPGA MRCC inputs of bank 14. This USER_CLOCK_P and
USER_CLOCK_N clock signal pair are connected to FPGA U1 pins AK34 and AL34
respectively. On power-up the user clock defaults to an output frequency of 156.250 MHz.
User applications can change the output frequency within the range of 10 MHz to
810 MHz through an I
2
C interface. Power cycling the VC707 board reverts the user clock to
its default frequency of 156.250 MHz.
• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz - 810 MHz)
• Differential Output
X-Ref Target - Figure 1-9
Figure 1-9: System Clock Source
UG885_c1_09_020612
GND
VCC2V5
SIT9102
200 MHz
Oscillator
OE
NC
GND
VCC
OUT_B
OUT
1
2
3
6
5
4
U51
R166
100Ω 1%
SYSCLK_P
SYSCLK_N
C30
0.1 μF 10V
X5R
Send Feedback

Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English