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Chapter 5 Theory of Operation
System DAC
5
System DAC
See “A1 System DAC Schematic” on page 191.
The System DAC provides dc voltages that control various parameters
of the instrument’s operation. This schematic page also includes analog
multiplexers that select various signals for measurement by the A/D
Converter.
The System DAC U701 is loaded with serial data from the Main Gate
Array, U302, using SYSDAC_CLK, SYSDAC_STRB*, and
SYSDAC_DATA. The DAC’s voltage reference is 2.5 V, provided by
U601, and its nominal output ranges from 0 V to +2.5 V. The DAC’s
output is buffered and amplified to a ±2.5 V range by U702-A and
applied to multiplexer U703.
Each switch in U703, along with an associated holding capacitor (C701
through 703, C707, and C709 through C712) and a buffer amplifier
(U704, U705, U1601-B, and U1603-B), makes up a track-and-hold circuit
whose output is a control voltage. In operation, SYSDAC_SEL(2:0)
(from U302) are driven to select one of the track-and-hold circuits, and
the DAC is loaded with a corresponding value. After allowing 1.5 µs for
the DAC to settle, the selected channel of the multiplexer is closed by the
assertion of SYSDAC_SMPL and the holding capacitor is driven to
U702-A’s output voltage. After 12.7 µs, SYSDAC_SMPL is negated and
process repeats for the next track-and-hold. All channels are
continuously refreshed in this manner by hardware in U302 and U202.
Multiplexers U706, U707, and U708 switch various measurement
signals into three output lines (MEAS1, MEAS2, and MEAS3).
These lines are applied to multiplexer U603 and are used to monitor the
instrument’s output and measure signals for self-test and calibration.
U703 Output Channel Function Range
0 V_CONTRAST Sets the display viewing angle. 0 to +5 V
1 V_NULL Nulls the multiplier input offset voltage. ±2.5 V
2 V_AMPL Sets the output amplitude. ±2.5 V
3 V_OFFSET Sets the output offset. ±2.5 V
4 V_LEDGE Sets the pulse leading edge time. 0 to +2.5 V
5 V_TEDGE Sets the pulse trailing edge time. 0 to –2.5 V
6 V_THRESH Sets the square wave duty cycle. ±2.5 V
7 V_TBCAL Sets the timebase frequency. 0 to +5 V
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