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Chapter 5 Theory of Operation
Trigger and Delay
5
Trigger and Delay
See “A1 Trigger Schematic” on page 194.
The instrument has a bi-directional, chassis referenced, TTL trigger
BNC connector. Triggering can occur either from the external trigger
BNC input or from the instrument’s internal trigger. The user can elect
to send the instrument’s internal trigger out the trigger BNC connector
to synchronize other instruments.
External trigger inputs are buffered by U1002-A and applied to the
opto-isolator U1003. U1002-A has a small amount of positive feedback
through R1019 to provide hysteresis. U1004-A converts the external
trigger to ECL voltages.
When the internal trigger is selected and a trigger out is desired, the
TRIG_OUT signal provides the trigger out. This signal is opto-isolated by
U1001 and applied to three-state buffers, U1002-B, C, D which provide
the current drive for the external trigger. TRG_OUT_EN* from U105
enables the outputs of U1002-B, C, D.
U1005-A, U1005-B, and U1005-C are AND gates whose outputs are
connected together to form the trigger input selector. Either slope of the
external input (EXT_TRG+ or EXT_TRG–) or the internal trigger signal
(INT_TRG) can be selected by asserting the proper enable signal
(EXT_TRG+_EN, EXT_TRG–_EN, INT_TRG_EN). U1005-D ensures
that the instrument cannot be triggered unless triggers are enabled
(TRG_CTL(0) is high) and the synthesizer is stopped.
A variable trigger-delay circuit consisting of U12004-B, U1006 through
U1009, and associated components is used to synchronize the synthesizer to
the selected trigger. This circuit can provide up to 40 ns of delay with
approximately 10 ps resolution. Trigger delays up to 85 seconds are
achieved by counting clocks in the Synthesis IC, and then interpolating
between the clocks with this circuit.
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