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Chapter 5 Theory of Operation
Synthesis IC
4
5
Digital Circuitry
The digital circuitry contains all the waveform generation circuitry and
waveform memory. The main CPU and communications CPU (outguard)
are also included.
Synthesis IC
See “A1 Synthesis IC Schematic” on page 196.
U1201 is an SRAM-based field-programmable gate array that implements
most of the logic for waveform generation. The Main Processor loads data
into U1201 from main memory to implement one of two “personalities”:
DDS waveform generation or Pulse waveform generation.
The instructions are loaded into the Synthesis IC at wakeup or when
the instrument’s output mode is changed between DDS and Pulse.
The instructions are loaded via a serial interface using SYN_CLK,
SYN_STATUS*, SYN_CONFIG*, SYN_CONFDONE, and SYN_DATA0.
The Synthesis IC interfaces to the DSP and Main Processor through a
shared 16-bit bus (SHR_D(0:15) and SHR_A(0:15)).
The analog-to-digital converter sends serial data to U1201 using
ACD_SDATA, ADC_SCLK, and ADC_DRDY. The 15-MHz ADC_SCLK
clocks the data during the first half of the 32-cycle analog-to-digital
conversion cycle. ADC_DRDY marks the beginning of a new word and
synchronizes the internal shift register.
U1201 has two identical DAC interfaces, DAC0 and DAC1. DAC0 (U607)
is used for frequency-response leveling and amplitude modulation,
as well as fine delay for pulses. DAC1 (U1009) is the fine control for the
trigger delay.
Data is sent to the triggered phase lock loop (U904) through a serial
interface using TRG_DCLK, TRG_DATA, TRG_STRB. The VCO(0:6)
lines are used by U907 to coarsely set the triggered VCO’s frequency.
The main Synthesis IC clock is CLK_d4. This is the 200 MHz clock
divided by 4 (50 MHz). A second clock, CLK_d2, provides a 100 MHz
clock used by the Synthesis IC to “accelerate” the waveform addresses.
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