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Chapter 5 Theory of Operation
Synchronous Multiplexer
4
5
Synchronous Multiplexer
See “A1 Synchronous Multiplexer Schematic” on page 198.
Waveform data from the Waveform RAM is converted from TTL levels
to ECL levels using resistive dividers (R1402 through R1413, R1417
through R1428, R1437 through R1448, and R1455 through R1466).
The control signals from U1202 are converted from TTL to ECL by
U1402 and U1403.
U1404 through U1407 form a pipeline stage clocked at 100 MHz by
CLK_d2e. U1408 and U1409 interleave “even” and “odd” data from
U1404 through U1406 into a single 200 MHz data stream, WFD(11:0),
for the Waveform DAC. Similarly, “even” and “odd” signals from U1407
are interleaved by U1410. U1408 through U1410 are registers, clocked at
200 MHz by LOGIC_CLK, with input multiplexers that are controlled by
EVN_nODD (derived from CLK_d2e).
In normal operation, “even” waveform data is fed to the registers with
CLK_d2e is high, and “odd” data is selected when CLK_d2e is low.
However, U1401-D and U1401-C can override the state of CLK_d2e and
force EVN_nODD to be high or low, depending upon the states of
EVN_ONLY and ODD_ONLY (from U1201). Asserting EVN_ONLY
causes data from the “odd” waveform memory to be ignored, allowing the
memory to be accessed by the main processor or DSP while the system is
running. Similarly, asserting ODD_ONLY allows the “even” memory to
be accessed. Certain parameters, such as burst phase and ramp symmetry,
are modified by re-writing waveform memory while the system is running.
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