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Chapter 5 Theory of Operation
DSP and Gateway
5
DSP and Gateway
See “A1 DSP Schematic” on page 189.
U506 is the digital signal processor. It is clocked at 40.96 MHz from
U505. The DSP RAM, U507, is loaded by the Main CPU through the
gateway. U506 also communicates with the main CPU via a serial
connection, assisted by U302.
The bus gateway is controlled by the Main CPU U302. The gateway uses
U501, U502, U503, and U504 to allow the Main CPU to load the DSP
RAM (U507) and then isolates the two busses so the DSP can operate
independently of the main CPU.
The DSP has no ROM and instructions are loaded by the main CPU.
Earth-Referenced Logic
See “A1 Earth Referenced Communications Schematic” on page 185.
The earth-referenced logic provides triggers and communications.
Microprocessor U105 handles GPIB (IEEE-488) control through bus
interface chip U109 and bus receiver and driver chips U110 and U111.
U105 also controls the RS-232 interface through UART U106 and
transceiver chips U107 and U108. U107 and U108 provide the required
level shifting between the RS-232 ±9 V levels and the +5 V logic levels by
internal charge pumping circuits using capacitors C104 and C110.
Communication between the main CPU and the earth-referenced logic is
through an optically-isolated, bi-directional serial interface, U102 and U201.
U101 provides an independent reset of the floating microprocessor based
upon the +5_ER supply. The chassis ground and earth-referenced logic
ground (IOCOM) are dc coupled through transformer T101. IO Power
(IOVCC) is derived from the earth-referenced power supply (+5_ER)
through T101. T101 acts as a balun to reduce EMI.
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