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Chapter 5 Theory of Operation
Main Processor
5
Main Processor
See “A1 Main Processor Schematic” on page 186.
U202 is the main CPU for the instrument. U214 provides the 18 MHz
clock for the main CPU. The main CPU incorporates a number of on-chip
peripherals including:
• Asynchronous serial communications (UART)
• Autonomous synchronous serial communications (QSPI)
• Programmable periodic interrupt timer (PIT)
• 16-channel intelligent timer/counter (TPU)
Reset circuit U401 (shown on schematic 4) is the main CPU reset and
power failure circuit. U401 performs three functions:
1. Generates a shutdown on power fail.
2. At power up, ensures the clocks and CPU have stable power before
the CPU starts running.
3. Prevent multiple turn-on/turn-off cycles during unstable power
conditions by keeping RESET* asserted until power is steady.
The PWR_FAIL* signal from the main power supply indicates when
ac power has been lost. When PWR_FAIL* is asserted, U401 asserts
ACFAIL* for approximately 4 ms and then asserts RESET* for a timed
minimum duration or until power completely fails. The ACFAIL* signal
is applied to the CPU IRQ6 input and instructs the main CPU to save
the current state in non-volatile memory. The RESET* signal suspends
main CPU operation. The main CPU wake-up configuration is set by
R228 through R235.
The main CPU uses seven chip select lines; CS0 through CS5 and
CSBOOT. These lines select the RAM, FRAM, and Flash ROM when
appropriate. ROMs U207, U208, U209, and U210 are each 512k x 8,
providing 1 Meg of 16-bit words. U203 and U204 are 512k x 8 SRAM
chips, providing 512 k-words of 16-bit RAM space. U211 is a ferro-
electric RAM used to store non-volatile calibration coefficients and the
power-on state of the instrument.
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