116
Chapter 5 Theory of Operation
Phase Locked Loops
5
Phase Locked Loops
See “A1 Phase-Locked Loops Schematic” on page 193.
There are two phase locked loops (PLLs). A primary PLL, which
ultimately furnishes the clocks for DDS waveforms, and a triggered PLL,
which is used in pulse generation.
The primary PLL multiplies the 10 MHz frequency reference to 800 MHz.
The PLL synthesizer, U901, is programmed at power on using the serial
transfer lines PRI_DATA, PRI_DCLCK, and PRI_STRB from the Main
Processor U202. The frequency reference, PRI_FREF, is obtained from
U804 in the timebase circuits.
Voltage controlled oscillator, U903, can be tuned from 797 MHz to 803 MHz.
Part of the 800 MHz output is fed back to the PLL synthesizer and
phase-compared to the reference frequency.
U901 asserts PRI_LOCK when the PLL is locked. This signal is used by
the main processor (and can be reported to the front panel display and
the GPIB status byte).
U902 buffers the VCO control voltage and sends it through U707 to be
measured during self-test. Q901 provides a means to turn off U903 for testing.
The triggered phase lock loop is programmed by the Synthesis IC
through lines TRG_DCLK, TRG_STRB, and TRG_DATA. The 25 MHz
frequency reference is derived from the 800 MHz clock by U1101, U1102,
and U1103. The triggered PLL is tuned from 100 MHz to 200 MHz in
2kHz steps.
To Next Page
Loading...
Need help?
General
