CHAPTER 3: INSTALLATION PILOT CHANNEL COMMUNICATIONS
L90 LINE CURRENT DIFFERENTIAL SYSTEM – INSTRUCTION MANUAL 3-41
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3.4.4.3 Transmit timing
The RS422 interface accepts one clock input for transmit timing. It is important that the rising edge of the 64 kHz transmit
timing clock of the multiplexer interface is sampling the data in the center of the transmit data window. Therefore, it is
important to confirm clock and data transitions to ensure proper system operation. For example, the following figure
shows the positive edge of the Tx clock in the center of the Tx data bit.
Figure 3-43: Clock and data transitions
3.4.4.4 Receive timing
The RS422 interface utilizes NRZI-MARK modulation code and therefore does not rely on an Rx clock to recapture data.
NRZI-MARK is an edge-type, invertible, self-clocking code.
To recover the Rx clock from the data-stream, an integrated digital phase lock loop (DPLL) circuit is utilized. The DPLL is
driven by an internal clock, which is 16-times over-sampled, and uses this clock along with the data-stream to generate a
data clock that can be used as the serial communication controller (SCC) receive clock.
3.4.5 Two-channel two-clock RS422 interface
The two-channel two-clock RS422 interface (module 7V) is for use with the synchrophasor feature. The figure shows the
module connections.
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