June 15, 2005 6815854H01-A
4-26 Troubleshooting Procedures: 700–800 MHz Main Board Troubleshooting
Figure 4-11. Frequency Generation Unit Block Diagram (700–800 MHz)
Table 4-15. LV Frac-N U6751 Pin Descriptions (700–800 MHz)
Pin No. Pin Name Description
1
AUX2 Auxiliary logic output, high selects U6754 OSC2
2
AUX3 Auxiliary logic output, high selects U6755 OSC1
3
AUX4 Auxiliary logic output, high selects U6755 OSC2
4
LOCK Lock detect—logic high indicates in-lock condition
5
PD_VDD 3.0-V supply (phase detector)
6
GROUND Ground (digital)
7
DATA SPI data I/O
8
CLK SPI clock
9
CEX SPI enable line—active low
10
MODIN Modulation input from controller
11
VMULT4 Multiplier clock output
12
VMULT3 Multiplier clock output
Bias 1
3.0V
3.0V
3.0V
3.0V
8.2V
8.2V
8.2V
Q6753
Q6755
Q6756
Q6760
Lock Detect
to Controller
Prescaler Input
Q6761
RF
Feedback
RX
INJECTION
TX
INJECTION
RX
Injection
TX
Injection
Keyed
9.1V
U6754
U6755
8.2V
C6783
LOOP
FILTER
Bias 2
9.3V
9.3V
SFIN
SFBASE
SFOUT
Lock
PREIN
AUX4
AUX3
Mod Out
IADAPT
IOUT
AUX2
AUX1
VMULT4
VMULT3
5.0V
16.8MHz Reference
to Controller and
Receiver Back End
VOLTAGE
MULTIPLIER
D6751 and
D6752
16.8MHz OSC
8.2V
Super Filter
Q6759
8.2V SW
8.2V SW
8.2V SW
8.2V SW
U6752
U6751
3.0V
Regulator
U6750
PHASE
DETECTOR BIAS
Q6757 RX and
Q6758 TX
CLOCK
SYN_SEL
DATA
MOD_IN
From
Controller
MAEPF-27804-O
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