June 15, 2005 6815854H01-A
3-24 Theory of Operation: Receiver Back-End
Figure 3-18. ABACUS III (AD9874) IC Functional Block Diagram from Data Sheet (VHF)
3.11.1.2.1 Second Local Oscillator
The ABACUS III IC local oscillator (LO) synthesizer controls the second LO. Signal FREF is the
16.8 MHz reference from the frequency generation unit (FGU). The second LO frequency is
107.4 MHz by default, or 111.9 MHz in special cases as necessary to avoid radio self-quieters. The
second LO signal mixes with IFIN to produce a 109.65 MHz final IF. The external VCO consists of
transistor Q3000, together with its bias and instability network and tank elements. Darlington
transistor Q3001 along with C3035 and C3017 form an active DC filter. The second-order loop filter
is comprised of C3044, C3005, and R3009.
3.11.1.2.2 Sampling Clock Oscillator
The ABACUS III IC sampling clock synthesizer, at Fclk=18 MHz (IF2=Fclk/8, where Fclk is the clock
rate), utilizes a negative-resistance core that is internal to the ABACUS III IC which, when used in
conjunction with an external LC tank (made up of L3003 and C3039) and a varactor (D3001), serves
as the VCO.
3.11.2 UHF Range 1 (380-470 MHz) Band
The receiver back-end (see Figure 3-15 on page 3-18) contains the following major components:
• Intermediate frequency (IF) filter
• ABACUS III IC
IFIN
FREF
-16dB
LNA
LO
Synth.
Sample Clock
Synthesizer
CLK VCO and
Loop Filter
LO VCOand
Loop Filter
Voltage
Reference
DAC AGC
ADC
Decimation
Filter
Formatting/SSI
Control Logic
f
CLK
= 13-26MHz
SPI
DOUTB
DOUTA
FS
CLKOUT
MXON
MXOP
IF2P
IF2N
GCP
GCN
LOP
IOUTL
LON
IOUTC
CLKP
CLKN
VREFP
VCM
VREFN
PC
PD
PE
SYNCB
MAEPF-27817-O
AD9874
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