Oki C9600 Service Manual

Oki Data CONFIDENTIAL
42930511TH Rev. 2 21 /
I2CROM
ASIC2
544pinPBAG
Xilinx FPGA
XC2S200E-6FT256C
256pinBGA
Xilinx FPGA
XC9572XL
100pinTQFP
LED
ASIC1
144pinPQFP
Parallel
74LVX161284
Engine
I/F
PCI
Slot
100pin
PCI
Slot
68pin
StepDownCont
MAX1718
5V to CVDD
PLVDD
Regulator
LT1764EQ
3.3V to 1.8V
Regulator
LTC3412EFE
5V to 2.5V
Regulator
LM2636
5V to 3.3V
Clock Generator
CY27EE16FZEC
Crystal oscillator
14.318MHz
Clock Generator
CY27EE16FZEC
Crystal oscillator
14.318MHz
256Kbit
Boot Flash
2Mbit
CompactFlash
Primary IDE
64MB
HDD 2.5inch
Secondary IDE
20GB
8Mbit Flash
CPU
TM5800
474pinCBGA
FAN Control
W83783S
CN
2kbit EEPROM
Microwire
SouthBridge
M1535+
353pinBGA
SDRAM DIMM
Clock Gen
RTC
Reset IC
MAX811
LEUS-T
0.75%
Center-spread
X’tal
14.318MHz
X’tal
30.000
MHz
nomount
EEPROM
USB2.0
NET2280
120pinTQFP
X’tal
32.768MHz
Battery
Resident 256MByte
+3.3V
+3.3V
+3.3V
+3.3V
+2.5V
+3.3V +5.0V
+5.0V
+5.0V
+1.8V +3.3V
+3.3V +3.3V
+5.0V
+2.5V +3.3V
+1.8V +3.3V
+5.0V
+3.3V
+1.8V +2.5V +3.3V
+5.0V +5.0V
CVDD
PLLVDD
+3.3V
+3.3V +3.3V
+5.0V +5.0V
+2.5V
CVDD
PLLVDD
+2.5V +3.3V
+3.3V, 2.5V, CVDD, PLLVDD
S_A[12:0]
S_DQ[63:0]
C_A[12:0]
C_DQ[63:0]
SA[19:0]
XD[7:0]
P_DA[2:0]
P_DD[15:0]
S_DA[2:0]
S_DD[15:0]
CPU_CLK 66MHz
CPU Sideband PCI_AD[31:0]
BRDATA0[31:0] BRDATA1[31:0] BRDATA2[31:0] BRDATA3[31:0]
PCICLK5
PCICLK6
IEEE1284
Connector
USB
Connector
PCICLK1
HW_RESET-N
PCICLK
HW_
RESET-N
MCLK_SRAM
0/1/2/3
MCLK_VXP
ICLK_VXP
VIDEO_0/1/2/3
LPC BUS
VCLK0/1
VCLK2 SERIAL-
CLK
WDATA0/1/2/3
PCICLK2
COREGOOD
PCICLK3
ENG_CLK
0
ENG_CLK
1
PCI_CLK_CPU 33MHz
CLK14MCLK48M
PCI_CLK_SB=33MHz
PCI_CLK[6:0]
XD[7:0]
HW_RESET-N
+2.5V
512Mbit
DDR
SDRAM
1
1
2
2
3
4
Resident
4MByte
8Mbit
PIPELINED
SRAM
1
2
3
4
2.1 Main Control PCB
Main Control PCB (ASP-PWB) (1200dpi)
Figure 2-1-1 illustrates the block diagram of the Main Control PCB (ASP PWB).
Figure 2-1-1

Oki C9600 Specifications

General

Brand	Oki
Model	C9600
Category	All in One Printer
Language	English